III-N heterostructure devices for low-power logic

Abstract

Future generations of ultra-scaled logic may require alternative device technologies to transcend the limitations of Si CMOS; in particular, power dissipation constraints in aggressively-scaled, highly-integrated systems make device concepts capable of achieving switching slopes (SS) steeper than 60 mV/decade especially attractive. Tunneling field effect transistors (TFETs) are one such device technology alternative. While a great deal of research into TFETs based on Si, Ge, and narrow band gap III-Vs has been reported, these approaches each face significant challenges. An alternative approach based on the use of III-N wide band gap semiconductors in conjunction with polarization engineering offers potential advantages in terms of drain current density and switching slope. In this talk, the prospects for III-N based TFETs for logic will be discussed, including both simulation projections as well as experimental progress.