Differential heating/cooling chip joining method to prevent chip package interaction issue in large die with ultra low-k technology

K. Sakuma, K. Smith, K. Tunga, E. Perfecto, T. Wassick, F. Pompeo, J. Nah
{"title":"Differential heating/cooling chip joining method to prevent chip package interaction issue in large die with ultra low-k technology","authors":"K. Sakuma, K. Smith, K. Tunga, E. Perfecto, T. Wassick, F. Pompeo, J. Nah","doi":"10.1109/ECTC.2012.6248866","DOIUrl":null,"url":null,"abstract":"A differential heating/cooling chip join method was developed for Pb-free flip chip packaging of ultra low-k (ULK) technology Si chips on organic substrates to prevent Chip-Package Interaction (CPI) - related damage upon chip joining. A chip was mounted to a bonder head and a substrate was located on a base plate and they were held at different elevated temperatures during the bonding process. The temperature difference between the Si chip and the organic substrate during assembly provides a substantially matched thermal expansion and minimizes stress induced by coefficient of thermal expansion (CTE) mismatch. From the modeling study, it was confirmed that chip warpage, Controlled Collapse Chip Connection (C4) stresses/strains, and ULK stresses decreased significantly by differential heating/cooling chip join method, with further improvement noted as the substrate temperature was decreased during the bonding process. X-ray, scanning electron microscope (SEM) and C-mode scanning acoustic microscope (C-SAM) were used to examine the defects after flip chip assembly. Noncontact white light reflectometry was also used to measure the warpage shape of the assembled silicon chip and the organic substrate. Observation under C-SAM indicated that fractures in the ULK layers were dramatically reduced by the differential heating/cooling chip joining process compared to the conventional reflow process. Non-destructive X-ray images indicated there were no solder bridging in any area of the chip interconnects. The experimental results showed that the differential heating/cooling chip join process can effectively reduce fractures in the ULK layers and prevent C4 bump bridging in a large die package with low-K dielectric constant device integration and high Ag content solder bumps.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE 62nd Electronic Components and Technology Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.2012.6248866","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 19

Abstract

A differential heating/cooling chip join method was developed for Pb-free flip chip packaging of ultra low-k (ULK) technology Si chips on organic substrates to prevent Chip-Package Interaction (CPI) - related damage upon chip joining. A chip was mounted to a bonder head and a substrate was located on a base plate and they were held at different elevated temperatures during the bonding process. The temperature difference between the Si chip and the organic substrate during assembly provides a substantially matched thermal expansion and minimizes stress induced by coefficient of thermal expansion (CTE) mismatch. From the modeling study, it was confirmed that chip warpage, Controlled Collapse Chip Connection (C4) stresses/strains, and ULK stresses decreased significantly by differential heating/cooling chip join method, with further improvement noted as the substrate temperature was decreased during the bonding process. X-ray, scanning electron microscope (SEM) and C-mode scanning acoustic microscope (C-SAM) were used to examine the defects after flip chip assembly. Noncontact white light reflectometry was also used to measure the warpage shape of the assembled silicon chip and the organic substrate. Observation under C-SAM indicated that fractures in the ULK layers were dramatically reduced by the differential heating/cooling chip joining process compared to the conventional reflow process. Non-destructive X-ray images indicated there were no solder bridging in any area of the chip interconnects. The experimental results showed that the differential heating/cooling chip join process can effectively reduce fractures in the ULK layers and prevent C4 bump bridging in a large die package with low-K dielectric constant device integration and high Ag content solder bumps.
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采用超低k技术,采用差分加热/冷却芯片连接方法,防止大型芯片封装相互作用问题
针对有机衬底上超低k (ULK)技术Si芯片的无铅反转封装,提出了一种不同的加热/冷却芯片连接方法,以防止芯片连接时芯片封装相互作用(CPI)相关的损伤。将芯片安装在粘合头上,将基板置于基板上,并在粘合过程中保持在不同的高温下。在组装过程中,硅片和有机衬底之间的温差提供了基本匹配的热膨胀,并将热膨胀系数(CTE)不匹配引起的应力降至最低。从建模研究中可以证实,通过不同的加热/冷却芯片连接方法,芯片翘曲、可控崩溃芯片连接(C4)应力/应变和ULK应力显著降低,并且随着结合过程中衬底温度的降低,进一步改善。采用x射线、扫描电镜(SEM)和c模扫描声显微镜(C-SAM)对倒装芯片组装后的缺陷进行了检测。非接触式白光反射法还用于测量组装硅芯片和有机衬底的翘曲形状。C-SAM观察表明,与常规回流工艺相比,采用不同的加热/冷却芯片连接工艺可以显著减少ULK层的裂缝。非破坏性x射线图像显示,在芯片互连的任何区域都没有焊接桥接。实验结果表明,在具有低k介电常数器件集成和高Ag含量焊料凸点的大型晶片封装中,采用不同的加热/冷却芯片连接工艺可以有效减少ULK层的断裂,防止C4凸点桥接。
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