G. Bollati, A. Dati, G. Betti, I. Bietti, F. Brianti, M. Bruccoleri, M. Coltella, P. Demartini, M. Demicheli, P. Gadducci, Stefano Marchese, D. Ottini, Valerio Pisati, F. Rezzi, A. Rossi, P. Savo, C. Tonci, R. Castello
{"title":"A 450 Mbit/s parallel read/write channel with parity check and 16-state time variant Viterbi","authors":"G. Bollati, A. Dati, G. Betti, I. Bietti, F. Brianti, M. Bruccoleri, M. Coltella, P. Demartini, M. Demicheli, P. Gadducci, Stefano Marchese, D. Ottini, Valerio Pisati, F. Rezzi, A. Rossi, P. Savo, C. Tonci, R. Castello","doi":"10.1109/CICC.2000.852676","DOIUrl":null,"url":null,"abstract":"A PRML read/write IC operating up to 450 Mbit/s is presented. The chip implements a 16-state EPR4 parity check time variant Viterbi detector and a digital servo. A 24/26 code with parity check improves the robustness to white noise, media noise and to off-track conditions. The device is integrated in a mature 0.35 /spl mu/m BiCMOS technology with a die size of 13 mm/sup 2/ (step and repeat) and dissipates 1.9 W (in read mode) at 450 Mbit/s.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"24 1","pages":"319-322"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2000.852676","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A PRML read/write IC operating up to 450 Mbit/s is presented. The chip implements a 16-state EPR4 parity check time variant Viterbi detector and a digital servo. A 24/26 code with parity check improves the robustness to white noise, media noise and to off-track conditions. The device is integrated in a mature 0.35 /spl mu/m BiCMOS technology with a die size of 13 mm/sup 2/ (step and repeat) and dissipates 1.9 W (in read mode) at 450 Mbit/s.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
