A W-Band transmitter channel with 16dBm output power and a receiver channel with 58.6mW DC power consumption using heterogeneously integrated InP HBT and Si CMOS technologies

Ahmed S. H. Ahmed, A. Simsek, A. Farid, A. Carter, M. Urteaga, M. Rodwell
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引用次数: 4

Abstract

We report a high output power transmitter and a low DC power receiver front-end channels of a phased array transceiver, designed in heterogeneously integrated 250 nm InP HBT and 130 nm Si CMOS technologies. The transmitter channel consists of a variable gain amplifier, an IQ-vector-modulator-based phase shifter, and a power amplifier. External Analog control signals are used to adjust the phase shifter and VGA states. The transmitter has a saturated output power of 16dBm at 90GHz while consuming 885mW DC power. The receiver channel uses a low noise amplifier with a similar phase shifter, and a variable gain amplifier. 4-bit DACs are implemented in the CMOS to control the phase shifter and VGA. The overall the receiver channel has ~26dB small signal gain at 58.6 mW DC power dissipation. The areas of the transmitter and receiver channels are 2.7x0.81mm2 and 2.1x0.76mm2 respectively.
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采用异构集成的InP HBT和Si CMOS技术,实现了输出功率为16dBm的w波段发射通道和直流功耗为58.6mW的接收通道
我们报道了一种高输出功率发射器和低直流功率接收器的相控阵收发器前端通道,采用异质集成250纳米InP HBT和130纳米Si CMOS技术设计。发射信道由可变增益放大器、基于iq矢量调制器的移相器和功率放大器组成。外部模拟控制信号用于调整移相器和VGA状态。发射机在90GHz时的饱和输出功率为16dBm,而直流功耗为885mW。接收通道使用具有类似移相器的低噪声放大器和可变增益放大器。在CMOS中实现4位dac来控制移相器和VGA。总体而言,接收通道在58.6 mW直流功耗下具有~26dB的小信号增益。发射信道面积为2.7x0.81mm2,接收信道面积为2.1x0.76mm2。
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