A 2.4-5.25GHz Balun-LNA in 22nm CMOS Technology

Abstract

This paper presents a $2.4\sim 5.25{\mathrm {GHz}}$ single to differential low-noise amplifier (balun-LNA) using 22nm CMOS technology. Current-reuse technique is introduced to make a compromise between gain and linearity. A balanced buffer is used to reduce the gain difference and phase difference of the differential outputs. The contradiction between linearity and NF can also be resolved through variable gain control. The post-simulation results show that it achieves a voltage gain of 30. 0dB, an NF of 1. 49dB, the phase mismatch of 0.3°, and the gain mismatch of 0.1 dB in the high-gain mode. The IIP3 is 9. 0dBm, and IP1dB is 3.0 dBm in the low-gain mode. At 1V supply voltage, the power consumption is 1S.43mW, and the layout is 0.63mm2.