A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm2 cell in 32nm high-k metal-gate CMOS

Y. Fujimura, O. Hirabayashi, T. Sasaki, A. Suzuki, A. Kawasumi, Y. Takeyama, K. Kushida, G. Fukano, A. Katayama, Y. Niki, T. Yabe
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引用次数: 34

Abstract

This paper presents a configurable SRAM for low-voltage operation with constant-negative-level write buffer (CNL-WB) and level programmable wordline driver for single supply (LPWD-SS) operation. CNL-WB is suitable for compilable SRAMs and it improves write margin by featuring an automatic BL-level adjustment for configuration range of four to 512 cells/BL using a replica-BL technique. LPWD-SS optimizes the tradeoff between disturb and write margin of a memory cell, allowing a 60% shorter WL rise time than that of the conventional design [1] at 0.7V. A test-chip is fabricated in a 32nm high-k metal-gate CMOS technology with a 0.149µm2 6T-SRAM cell. Measurement results demonstrate a cell-failure rate improvement of two orders of magnitude for an array-configuration range of 64 to 256 rows by 64 to 256 columns.
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采用32nm高k金属栅极CMOS,采用0.149µm2电池,设计了一种具有恒定负电平写入缓冲器的可配置SRAM,用于低压操作
提出了一种具有恒负电平写入缓冲器(CNL-WB)和电平可编程字行驱动器(LPWD-SS)的低电压可配置SRAM。CNL-WB适用于可编译的sram,它通过使用复制-BL技术,在4到512个单元/BL的配置范围内自动调整BL水平,从而提高了写入余量。LPWD-SS优化了存储单元的干扰和写入裕度之间的权衡,在0.7V时,比传统设计[1]的WL上升时间缩短了60%。测试芯片采用32nm高k金属栅CMOS技术,具有0.149µm2的6T-SRAM单元。测量结果表明,对于64至256行× 64至256列的阵列配置范围,电池故障率提高了两个数量级。
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