New scan compression approach to reduce the test data volume

IF 1.1 4区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IET Computers and Digital Techniques Pub Date : 2021-03-18 DOI:10.1049/cdt2.12020

Pralhadrao V. Shantagiri, Rohit Kapur, Chandrasekar Shastry

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引用次数: 1

Abstract

The test data volume (TDV) increases with increased target compression in scan compression and adds to the test cost. Increased TDV is the result of a dependency across scan flip-flops (SFFs) that resulted from compression architecture, which is absent in scan mode. The SFFs have uncompressible values logic-0 and logic-1 in many or most of the patterns contribute to the TDV. In the proposed new scan compression (NSC) architecture, SFFs are analysed from Automatic Test Pattern Generation (ATPG) patterns generated in a scan mode. The identification of SFFs to be moved out of the compression architecture is carried out based on the NSC. The method includes a ranking of SFFs based on the specified values present in the test patterns. The SFFs having higher specified values are moved out of the compression architecture and placed in the outside scan chain. The NSC is the combination of scan compression and scan mode. This method decides the percentage (%) of SFFs to be moved out of compression architecture and is less than 0.5% of the total SFFs present in the design to achieve a better result. The NSC reduces dependencies across the SFFs present in the test compression architecture. It reduces the TDV and test application time. The results show a significant reduction in the TDV up to 78.14% for the same test coverage.

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新的扫描压缩方法，减少测试数据量

在扫描压缩中，随着目标压缩的增加，测试数据量(TDV)也随之增加，从而增加了测试成本。增加的TDV是扫描触发器(sff)依赖的结果，这是由压缩架构导致的，在扫描模式中不存在。在许多或大多数构成TDV的模式中，sff具有不可压缩值logic-0和logic-1。在新提出的扫描压缩(NSC)架构中，从扫描模式生成的自动测试模式生成(ATPG)模式分析sff。要移出压缩体系结构的sff的识别是基于NSC进行的。该方法包括基于测试模式中存在的指定值的sff排序。具有较高指定值的sff被移出压缩体系结构并放置在外部扫描链中。NSC是扫描压缩和扫描模式的结合。该方法决定了从压缩架构中移出的sff的百分比(%)，并且小于设计中存在的总sff的0.5%，以获得更好的结果。NSC减少了测试压缩体系结构中sff之间的依赖关系。它减少了TDV和测试应用时间。结果表明，对于相同的测试覆盖率，TDV的显著降低高达78.14%。

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来源期刊

IET Computers and Digital Techniques 工程技术-计算机：理论方法

CiteScore

3.50

自引率

0.00%

发文量

审稿时长

>12 weeks

期刊介绍： IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.