K. Tomobe, T. Takahashi, M. Kawashima, Y. Sonobe, T. Kiyuna, S. Yamamoto
{"title":"A 1860 kG CMOS gate array with GTL input flip-flop circuits","authors":"K. Tomobe, T. Takahashi, M. Kawashima, Y. Sonobe, T. Kiyuna, S. Yamamoto","doi":"10.1109/CICC.1996.510512","DOIUrl":null,"url":null,"abstract":"A 1860 kG CMOS gate array with a high speed I/O circuit using 0.35 /spl mu/m CMOS process technology, has been developed. 300 MHz synchronous data transmission through a 30 cm line has been achieved with a flip-flop circuit which can directly receive and store a low voltage swing signal. This circuit technique reduces the latency time of data transmission between 2 LSIs by as much as 1.7 ns compared with conventional circuits.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"106 1","pages":"61-64"},"PeriodicalIF":0.0000,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1996.510512","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A 1860 kG CMOS gate array with a high speed I/O circuit using 0.35 /spl mu/m CMOS process technology, has been developed. 300 MHz synchronous data transmission through a 30 cm line has been achieved with a flip-flop circuit which can directly receive and store a low voltage swing signal. This circuit technique reduces the latency time of data transmission between 2 LSIs by as much as 1.7 ns compared with conventional circuits.
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