A hierarchy multiple-voltage design technique for low-power performance-manageable bio-chips

Abstract

A Hierarchy Multiple-Voltage (HMulti-Vdd) design technique is proposed in this paper which can effectively reduce power consumption. This paper presents an EDA automation design flow that facilitates separation of high-voltage and low-voltage module in synthesis stage. The proposed HMulti-Vdd methodology can be utilized to identify how many voltage domain and how low supplied voltage are better to design a low-power chip, while include the performance estimation. The HMulti-Vdd software tool includes a low-power multi-Vdd chip design optimization process and joint with several commercial circuit synthesis, physical design tools. Using HMulti-Vdd, the designed module voltage assignment is based on power, delay-time and gate-count analysis. HMulti-Vdd can help designer to reduce the Multi-Vdd design manually efforts. For several designed bio-chips have been validates by using this tool, the power consumption can be effectively reduced up to 50%, and the performance loss can be controlled within 5%.