TC degradation and root-cause analysis of SACVD BPSG film for robust IC fabrication

Abstract

Enhanced etch rate in the phosphorus enriched area in PTEOS/BPSG stacked interlayer dielectric (ILD) during contact open process were shown to have tungsten notch and micro-crack nucleation at the interface. Subsequent CVD TiN and W deposition can lead to penetration into this micro-crack that can lead to delamination after temperature cycling (TC) stress test. The notch defect was a result of higher etch rate at the PTEOS/BPSG interface due to high phosphorous concentration and profile associated with intrinsic process parameters and SACVD equipment. With further process optimization and tight process control, such defect free and robust production has been archived. Detailed failure mechanism using TEM and TOF-SIMS analyses and critical process parameters will be discussed and then intrinsic attributes of the SACVD equipment will be presented.