Design of High Performance IEEE754 Floating Point Multiplier Using Vedic Mathematics

Abstract

The fundamental and the core of all the Digital Signal Processors (DSPs) are its multipliers and the speed of the DSPs is mainly determined by the speed of its multiplier. In this paper we have synthesized and verified IEEE 754 single and double precision High Speed Floating Point Multiplier using VHDL on Xilinx Virtex - 5 FPGA. The Urdhva-Tiryakbhyam sutra (method) was selected for designing of mantissa. In addition the proposed designed handled underflow, overflow and rounding condition. High speed is achieved by reducing carry propagation delay by using carry save adder while implementation of four (27 × 27 bit multiplier for double precision) and (12 × 12 bit multiplier for single precision).