An Efficient Implementation of Pseudo Chaotic Sequences (PCS) Using Vedic Mathematics in DS-SS.

Abstract

In the wireless communication system security and content privacy of user data is of prime importance. In military application to provided security to the message signal and to overcome the interference problem,  we develop the use of pseudo-chaotic sequence (PCS) for spreading digital data in DS-SS (Direct Sequence Spread Spectrum). PCS belongs to the class of Non Linear Feedback Shift Register(NLFSR).The generation of PCS is done using multiplier. In order to reduce processing delay and to consume memory storage during sequence generation we adopted the concept of Vedic multiplier in this paper. The whole Vedic mathematics uses 16 sutras (formulas). Among the various method of multiplication Uardhava tiryakbhyam (vertically and crosswise) is discussed in details. It enables the parallel generation of partial products and eliminates unwanted multiplication steps. The modeled is proposed using VHDL and synthesis is done using Xilinx ISE 9.1 simulator.