{"title":"Design methodology of double nulling resistors nested-Miller compensation of multistage amplifier","authors":"Wing-Shan Tam, Chi-Wah Kok","doi":"10.1016/j.ssel.2018.06.001","DOIUrl":null,"url":null,"abstract":"<div><p>This paper presents a methodology to design large capacitive drive amplifier with high gain feed-forward transconductance stage using double nulling resistors nested-Miller compensation. The high gain-bandwidth and large phase margin of the amplifier can be obtained without stringent passive compensation components matching requirement, which enhances the design robustness towards process, voltage and temperature variations. The proposed amplifier circuit topology is simple and can be applied to implement amplifier with rail-to-rail input and output. A design example of three-stage rail-to-rail class-AB amplifier fabricated with 0.35-µ m 1P4M CMOS technology is presented. The performance of the fabricated amplifier is measured which shows the amplifier is suitable for high output drive applications.</p></div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"1 1","pages":"Pages 15-24"},"PeriodicalIF":0.0000,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/j.ssel.2018.06.001","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Solid State Electronics Letters","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S2589208818300061","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This paper presents a methodology to design large capacitive drive amplifier with high gain feed-forward transconductance stage using double nulling resistors nested-Miller compensation. The high gain-bandwidth and large phase margin of the amplifier can be obtained without stringent passive compensation components matching requirement, which enhances the design robustness towards process, voltage and temperature variations. The proposed amplifier circuit topology is simple and can be applied to implement amplifier with rail-to-rail input and output. A design example of three-stage rail-to-rail class-AB amplifier fabricated with 0.35-µ m 1P4M CMOS technology is presented. The performance of the fabricated amplifier is measured which shows the amplifier is suitable for high output drive applications.
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