3D System-on-Packaging Using Through Silicon Via on SOI for High-Speed Optcal Interconnections with Silicon Photonics Devices for Application of 400 Gbps and Beyond

Abstract

In this study, 3D electronic-photonic integrated circuits (EPIC) packaging using through silicon vias (TSV) has been demonstrated. Silicon photonic integrated circuit (Si-PIC) in SOI which has TSV for electrical interconnection is flip-chip bonded on a Si interposer using electrochemical plating (ECP) bumps of 90 µm-diameter in this 3D EPIC packaging. A 750 ?-cm of high-resistivity SOI and silicon wafers are used for PIC chip with TSV and interposer respectively. Measured insertion loss (S21) for the 3D EPIC packaged test vehicle using TSV is less than 3.5dB and return loss (S11) is less than -13dB up to 50 GHz. This high-bandwidth 3D EPIC packaging platform can be applied for the system-on-packaging (SOP) modules and subsystems such as optical transceiver (TRx) and radio-over-fiber (ROF) solutions.