LLHD: a multi-level intermediate representation for hardware description languages

Fabian Schuiki, Andreas Kurth, T. Grosser, L. Benini
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引用次数: 36

Abstract

Modern Hardware Description Languages (HDLs) such as SystemVerilog or VHDL are, due to their sheer complexity, insufficient to transport designs through modern circuit design flows. Instead, each design automation tool lowers HDLs to its own Intermediate Representation (IR). These tools are monolithic and mostly proprietary, disagree in their implementation of HDLs, and while many redundant IRs exists, no IR today can be used through the entire circuit design flow. To solve this problem, we propose the LLHD multi-level IR. LLHD is designed as simple, unambiguous reference description of a digital circuit, yet fully captures existing HDLs. We show this with our reference compiler on designs as complex as full CPU cores. LLHD comes with lowering passes to a hardware-near structural IR, which readily integrates with existing tools. LLHD establishes the basis for innovation in HDLs and tools without redundant compilers or disjoint IRs. For instance, we implement an LLHD simulator that runs up to 2.4× faster than commercial simulators but produces equivalent, cycle-accurate results. An initial vertically-integrated research prototype is capable of representing all levels of the IR, implements lowering from the behavioural to the structural IR, and covers a sufficient subset of SystemVerilog to support a full CPU design.
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硬件描述语言的多级中间表示
现代硬件描述语言(hdl),如SystemVerilog或VHDL,由于其纯粹的复杂性,不足以通过现代电路设计流程传输设计。相反,每个设计自动化工具都将hdl降低到自己的中间表示(IR)。这些工具都是单片的,大多是专有的,在实现hdl方面存在分歧,虽然存在许多冗余IR,但目前没有IR可以用于整个电路设计流程。为了解决这个问题,我们提出了LLHD多层红外光谱。LLHD设计为数字电路的简单,明确的参考描述,但完全捕获现有的hdl。我们用我们的参考编译器在像全CPU内核这样复杂的设计上展示了这一点。LLHD降低了接近硬件的结构红外通道,可以很容易地与现有工具集成。LLHD为hdl和工具的创新奠定了基础,没有冗余的编译器或不连接的ir。例如,我们实现了一个LLHD模拟器,其运行速度比商用模拟器快2.4倍,但产生相同的、周期精确的结果。最初的垂直集成研究原型能够表示IR的所有级别,实现从行为IR到结构IR的降低,并覆盖SystemVerilog的足够子集以支持完整的CPU设计。
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