Parallel Structure of All Digital Timing Synchronization and Realization of FPGA

Abstract

This paper focuses on the parallel implementation of high-speed and broadband transmission system, and proposes a low-complexity parallel structure, which is the integration of frequency domain timing synchronization and sample points shift. The study is on the basis of AVR Algorithm, which is able to satisfy different modulations. Different from the traditional feedback type all digital timing synchronization structure, the paper divides feedback timing adjustment into integer and fractional parts. The Algorithm of time domain sampling adjustment and frequency domain timing correction is designed and implemented on FPGA platform, and the simulation result verifies that the performance of this algorithm has 1dB gap compared with theoretical value in high-order modulation.