Distributed power semiconductor stress test & measurement architecture

Abstract

Conventional reliability testing of microelectronic power devices requires dedicated test systems. In order to test a statistically meaningful set of devices, only simplified stress pattern generation through a centralized controller is performed due to cost restrictions. Knowledge about device performance and failure time is commonly obtained by periodically removing the device from the test setup and performing a measurement on a different test hardware. In this paper, we propose a distributed power semiconductor stress test and measurement architecture to overcome limitations of existing test systems. We show that a local smart controller close to the tested device reduces the centralized system complexity by dividing the reliability testing problem into smaller tasks.