Two indirect methodologies for testing FPGA intrinsic Programmable Logic Cell timing performance

Abstract

Programmable Logic Cell (PLC) timing test is one of the most critical items for post-silicon validation of a new Field Programmable Gate Array (FPGA) product because it determines the fundamental performance of the FPGA chip. However, it has been very difficult to accurately measure all aspects of PLC segment timing for several practical reasons. First, some segments exhibit merely 100ps delay which places severe requirements on the resolution of the measurement system. Second, some segments are intrinsic elements in a FPGA and cannot be accessed directly from an external measurement port.