A High-Resolution Two-Step Time-to-Digital Conversion in 40 nm CMOS

Abstract

In this paper, a two-step Time-to-Digital converter (TDC) with a matching coarse-fine interface circuit for all-digital phase-locked loop (ADPLL) in a 40nm CMOS process is presented. A low-precision quantization architecture is used for the coarse stage of the designed two-step TDC to achieve wide dynamic range, and a high-precision quantization architecture is used for the fine stage to ensure higher resolution. A matching coarse-fine interface structure is proposed to reduce the transmission error. The simulation results show that the TDC can balance the performance of resolution, power consumption and dynamic range. The 32-level delay chain is used for the first-stage TDC with a quantization accuracy of 53. 8ps, and a 15-level delay chain with a quantization accuracy of 6. 2ps adopted in the second stage TDC. Under the condition that the reference frequency is 100MHz and its core chip size is $0.0431 mm^{2}$.