Enhancing fault sensitivity analysis through templates

Abstract

This paper gives an assessment of the threats posed by Fault Sensitivity Analysis attacks. We propose an overall discussion of the possibilities in attacking a hardware implementation of AES. The limitations of the current methodology are presented, together with new approaches that allow for more effective attacks. Utilizing gate level simulations, a comparison is performed of the performances of different variations of the attack methodology on different AES implementations. We also introduce the application of template attacks to the Fault Sensitivity Analysis. Results indicate that the use of templates helps to overcome some of the limitations of the original attack.