Pub Date : 2013-06-02DOI: 10.1109/HST.2013.6581579
Jeroen Delvaux, I. Verbauwhede
Physically Unclonable Functions (PUFs) are emerging as hardware security primitives. For so-called strong PUFs, the number of challenge-response pairs (CRPs) increases exponentially with the required chip area in the ideal case. They can provide a mechanism to authenticate chips which is inherently unique for every manufactured sample. Modeling of the CRP behavior through Machine Learning (ML) has shown to be a threat however. In this paper, we exploit repeatability imperfections of PUF responses as a side channel for model building. We demonstrate that 65nm CMOS arbiter PUFs can be modeled successfully, without utilizing any ML algorithm. Data originates from real-world measurements and hence not from simulations. Modeling accuracies exceeding 97% are obtained, which is comparable with previously published ML results. Information leakage through the exploited side channel should be considered for all strong PUF designs. Combined attack strategies, whereby repeatability measurements facilitate ML, might be effective and are recommended for further research.
{"title":"Side channel modeling attacks on 65nm arbiter PUFs exploiting CMOS device noise","authors":"Jeroen Delvaux, I. Verbauwhede","doi":"10.1109/HST.2013.6581579","DOIUrl":"https://doi.org/10.1109/HST.2013.6581579","url":null,"abstract":"Physically Unclonable Functions (PUFs) are emerging as hardware security primitives. For so-called strong PUFs, the number of challenge-response pairs (CRPs) increases exponentially with the required chip area in the ideal case. They can provide a mechanism to authenticate chips which is inherently unique for every manufactured sample. Modeling of the CRP behavior through Machine Learning (ML) has shown to be a threat however. In this paper, we exploit repeatability imperfections of PUF responses as a side channel for model building. We demonstrate that 65nm CMOS arbiter PUFs can be modeled successfully, without utilizing any ML algorithm. Data originates from real-world measurements and hence not from simulations. Modeling accuracies exceeding 97% are obtained, which is comparable with previously published ML results. Information leakage through the exploited side channel should be considered for all strong PUF designs. Combined attack strategies, whereby repeatability measurements facilitate ML, might be effective and are recommended for further research.","PeriodicalId":6337,"journal":{"name":"2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"27 1","pages":"137-142"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90363542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/HST.2013.6581580
J. Ju, R. Chakraborty, Charles Lamech, J. Plusquellic
Keying material for encryption is stored as digital bit-strings in non-volatile memory on FPGAs and ASICs in current technologies. However, secrets stored this way are not secure against a determined adversary, who can use probing attacks to steal the secret. Physical unclonable functions (PUFs) have emerged as an alternative. PUFs leverage random manufacturing variations as the source of entropy for generating random bit-strings, and incorporate an on-chip infrastructure for measuring and digitizing the corresponding variations in key electrical parameters, such as delay or voltage. PUFs are designed to reproduce a bitstring on demand and therefore eliminate the need for on-chip storage. In this paper, we evaluate the randomness, uniqueness and stability characteristics of a PUF based on metal wire resistance variations in a set of 63 chips fabricated in a 90 nm technology. The stability of the PUF and an on-chip voltage-to-digital converter are evaluated at 9 temperature-voltage corners.
{"title":"Stability analysis of a physical unclonable function based on metal resistance variations","authors":"J. Ju, R. Chakraborty, Charles Lamech, J. Plusquellic","doi":"10.1109/HST.2013.6581580","DOIUrl":"https://doi.org/10.1109/HST.2013.6581580","url":null,"abstract":"Keying material for encryption is stored as digital bit-strings in non-volatile memory on FPGAs and ASICs in current technologies. However, secrets stored this way are not secure against a determined adversary, who can use probing attacks to steal the secret. Physical unclonable functions (PUFs) have emerged as an alternative. PUFs leverage random manufacturing variations as the source of entropy for generating random bit-strings, and incorporate an on-chip infrastructure for measuring and digitizing the corresponding variations in key electrical parameters, such as delay or voltage. PUFs are designed to reproduce a bitstring on demand and therefore eliminate the need for on-chip storage. In this paper, we evaluate the randomness, uniqueness and stability characteristics of a PUF based on metal wire resistance variations in a set of 63 chips fabricated in a 90 nm technology. The stability of the PUF and an on-chip voltage-to-digital converter are evaluated at 9 temperature-voltage corners.","PeriodicalId":6337,"journal":{"name":"2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"15 1","pages":"143-150"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84292283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/HST.2013.6581570
Aydin Aysu, C. Patterson, P. Schaumont
The interest in lattice-based cryptography is increasing due to its quantum resistance and its provable security under some worst-case hardness assumptions. As this is a relatively new topic, the search for efficient hardware architectures for lattice-based cryptographic building blocks is still an active area of research. We present area optimizations for the most critical and computationally-intensive operation in lattice-based cryptography: polynomial multiplication with the Number Theoretic Transform (NTT). The proposed methods are implemented on an FPGA for polynomial multiplication over the ideal ℤp[x]〈xn + 1〉. The proposed hardware architectures reduce slice usage, number of utilized memory blocks and total memory accesses by using a simplified address generation, improved memory organization and on-the-fly operand generations. Compared to prior work, with similar performance the proposed hardware architectures can save up to 67% of occupied slices, 80% of used memory blocks and 60% of memory accesses, and can fit into smallest Xilinx Spartan-6 FPGA.
{"title":"Low-cost and area-efficient FPGA implementations of lattice-based cryptography","authors":"Aydin Aysu, C. Patterson, P. Schaumont","doi":"10.1109/HST.2013.6581570","DOIUrl":"https://doi.org/10.1109/HST.2013.6581570","url":null,"abstract":"The interest in lattice-based cryptography is increasing due to its quantum resistance and its provable security under some worst-case hardness assumptions. As this is a relatively new topic, the search for efficient hardware architectures for lattice-based cryptographic building blocks is still an active area of research. We present area optimizations for the most critical and computationally-intensive operation in lattice-based cryptography: polynomial multiplication with the Number Theoretic Transform (NTT). The proposed methods are implemented on an FPGA for polynomial multiplication over the ideal ℤp[x]〈xn + 1〉. The proposed hardware architectures reduce slice usage, number of utilized memory blocks and total memory accesses by using a simplified address generation, improved memory organization and on-the-fly operand generations. Compared to prior work, with similar performance the proposed hardware architectures can save up to 67% of occupied slices, 80% of used memory blocks and 60% of memory accesses, and can fit into smallest Xilinx Spartan-6 FPGA.","PeriodicalId":6337,"journal":{"name":"2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"1 1","pages":"81-86"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89193728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/HST.2013.6581565
R. P. Bastos, F. Sill, J. Dutertre, M. Flottes, G. D. Natale, B. Rouzeyre
This work presents a novel scheme of built-in current sensor (BICS) for detecting transient fault-based attacks of short and long duration as well as from different simultaneous sources. The new sensor is a single mechanism connected to PMOS and NMOS bulks of the monitored logic. The proposed protection strategy is also useful for improving any state-of-the-art Bulk-BICS from pairs of PMOS and NMOS sensors to single sensors.
{"title":"A bulk built-in sensor for detection of fault attacks","authors":"R. P. Bastos, F. Sill, J. Dutertre, M. Flottes, G. D. Natale, B. Rouzeyre","doi":"10.1109/HST.2013.6581565","DOIUrl":"https://doi.org/10.1109/HST.2013.6581565","url":null,"abstract":"This work presents a novel scheme of built-in current sensor (BICS) for detecting transient fault-based attacks of short and long duration as well as from different simultaneous sources. The new sensor is a single mechanism connected to PMOS and NMOS bulks of the monitored logic. The proposed protection strategy is also useful for improving any state-of-the-art Bulk-BICS from pairs of PMOS and NMOS sensors to single sensors.","PeriodicalId":6337,"journal":{"name":"2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"10 1","pages":"51-54"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86577412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/HST.2013.6581574
Jie Zhang, Q. Xu
There have been a number of hardware Trojan (HT) designs at register-transfer level (RTL) in the literature, which mainly describe their malicious behaviors and trigger mechanisms. Generally speaking, the stealthiness of the HTs is shown with extremely low sensitization probability of the trigger events. In practice, however, based on the fact that HTs are not sensitized with verification test cases (otherwise their malicious behaviors would have manifested themselves), designers could focus on verification corners for HT detection. Consequently, a stealthy HT not only requires to be hard to trigger, but also needs to be able to evade those hardware trust verification techniques based on “unused circuit identification (UCI)”. In this paper, we present new HT design and implementation techniques that are able to achieve the above objectives. In addition, attackers would like to be able to control their HTs easily, which is also considered in the proposed HT design methodology. Experimental results demonstrate that HTs constructed with the proposed technique are both hard to be detected and easy to be controlled when compared to existing HTs shown in the literature.
{"title":"On hardware Trojan design and implementation at register-transfer level","authors":"Jie Zhang, Q. Xu","doi":"10.1109/HST.2013.6581574","DOIUrl":"https://doi.org/10.1109/HST.2013.6581574","url":null,"abstract":"There have been a number of hardware Trojan (HT) designs at register-transfer level (RTL) in the literature, which mainly describe their malicious behaviors and trigger mechanisms. Generally speaking, the stealthiness of the HTs is shown with extremely low sensitization probability of the trigger events. In practice, however, based on the fact that HTs are not sensitized with verification test cases (otherwise their malicious behaviors would have manifested themselves), designers could focus on verification corners for HT detection. Consequently, a stealthy HT not only requires to be hard to trigger, but also needs to be able to evade those hardware trust verification techniques based on “unused circuit identification (UCI)”. In this paper, we present new HT design and implementation techniques that are able to achieve the above objectives. In addition, attackers would like to be able to control their HTs easily, which is also considered in the proposed HT design methodology. Experimental results demonstrate that HTs constructed with the proposed technique are both hard to be detected and easy to be controlled when compared to existing HTs shown in the literature.","PeriodicalId":6337,"journal":{"name":"2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"13 1","pages":"107-112"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90059339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/HST.2013.6581566
Li Li, H. Zhou
Obfuscation is a technique that makes comprehending a design difficult and hides the secrets in the design. An obfuscation is called best-possible if the obfuscated design leaks no more information than any other design of the same function. In this paper, we prove that any best-possible obfuscation of a sequential circuit can be accomplished by a sequence of four operations: retiming, resynthesis, sweep, and conditional stuttering. Based on this fundamental result, we also develop a key-based obfuscation scheme to protect design Intellectual Properties (IPs) against piracy. The novel obfuscation method embeds a secret key in the power-up state of IC, which is only known by the IP rights owner. Without the key, the IC still functions but its efficiency will be much degraded. Unlike existing IC metering techniques, the secret key in our approach is implicit thus it can also be used as a hidden watermark. Potential attacks and the countermeasures are thoroughly examined, and experimental results demonstrate the effectiveness of the method.
{"title":"Structural transformation for best-possible obfuscation of sequential circuits","authors":"Li Li, H. Zhou","doi":"10.1109/HST.2013.6581566","DOIUrl":"https://doi.org/10.1109/HST.2013.6581566","url":null,"abstract":"Obfuscation is a technique that makes comprehending a design difficult and hides the secrets in the design. An obfuscation is called best-possible if the obfuscated design leaks no more information than any other design of the same function. In this paper, we prove that any best-possible obfuscation of a sequential circuit can be accomplished by a sequence of four operations: retiming, resynthesis, sweep, and conditional stuttering. Based on this fundamental result, we also develop a key-based obfuscation scheme to protect design Intellectual Properties (IPs) against piracy. The novel obfuscation method embeds a secret key in the power-up state of IC, which is only known by the IP rights owner. Without the key, the IC still functions but its efficiency will be much degraded. Unlike existing IC metering techniques, the secret key in our approach is implicit thus it can also be used as a hidden watermark. Potential attacks and the countermeasures are thoroughly examined, and experimental results demonstrate the effectiveness of the method.","PeriodicalId":6337,"journal":{"name":"2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"58 1","pages":"55-60"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90973152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/HST.2013.6581575
Sheng Wei, M. Potkonjak
We develop a region-based timing characterization approach to detect hardware Trojans (HTs) on integrated circuits (ICs). In order to ensure the scalability of the approach, we partition the target IC into well-formed and non-overlapping regions and detect hardware Trojans on all circuit locations by examining the timing properties of the transistor paths. Based on the circuit partition, we insert a minimal number of test points that provide additional observation interfaces for the delay measurements of all circuit locations. Our evaluations on ISCAS and ITC benchmarks show that the region-based Trojan detection via test points can detect hardware Trojans accurately with well controlled area overhead and test time.
{"title":"Malicious circuitry detection using fast timing characterization via test points","authors":"Sheng Wei, M. Potkonjak","doi":"10.1109/HST.2013.6581575","DOIUrl":"https://doi.org/10.1109/HST.2013.6581575","url":null,"abstract":"We develop a region-based timing characterization approach to detect hardware Trojans (HTs) on integrated circuits (ICs). In order to ensure the scalability of the approach, we partition the target IC into well-formed and non-overlapping regions and detect hardware Trojans on all circuit locations by examining the timing properties of the transistor paths. Based on the circuit partition, we insert a minimal number of test points that provide additional observation interfaces for the delay measurements of all circuit locations. Our evaluations on ISCAS and ITC benchmarks show that the region-based Trojan detection via test points can detect hardware Trojans accurately with well controlled area overhead and test time.","PeriodicalId":6337,"journal":{"name":"2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"30 1","pages":"113-118"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91241467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/HST.2013.6581572
Vikram B. Suresh, D. Antonioli, W. Burleson
On-chip Random Number Generators (RNGs) are critical components in lightweight ubiquitous devices like RFIDs and smart cards. These devices require low cost test methodologies and security against cryptanalytic and invasive attacks. In this work we propose an on-chip implementation of a reduced set of NIST-SP-800-22 randomness test suite to provide on-line RNG testing for low cost security devices along with runtime monitoring of RNG performance. The on-chip NIST module monitors the effect of dynamic variation of operating condition and time dependent wear-out on RNG circuits. It indicates invasive attacks on RNG and allows the secure system to take protective measures. Six NIST tests are optimized to a hardware design friendly format, but in compliance with the NIST standard. The lightweight implementations reduce complex statistical and arithmetic operations of conventional NIST tests to a series of bit stream count and compare operations. A cycle-to-cycle serial test of incoming bits from RNG eliminates need for additional storage. A partial re-configurable feature is designed to set the pass/fail threshold for each test depending on the system requirements. The on-chip NIST module, although not exhaustive, is an effective layer of validation and security for RNG circuits. The six 128-bit tests implemented in 45nm NCSU PDK have a total synthesized area of ~1926.sq.um for an optimized frequency of 2GHz. The total dynamic power is 3.75mW and leakage power is 10.5μW. At 2Gbps, the NIST module consumes 1.87pJ/bit. The lightweight ultra-low power implementation is scalable for larger input bit samples.
{"title":"On-chip lightweight implementation of reduced NIST randomness test suite","authors":"Vikram B. Suresh, D. Antonioli, W. Burleson","doi":"10.1109/HST.2013.6581572","DOIUrl":"https://doi.org/10.1109/HST.2013.6581572","url":null,"abstract":"On-chip Random Number Generators (RNGs) are critical components in lightweight ubiquitous devices like RFIDs and smart cards. These devices require low cost test methodologies and security against cryptanalytic and invasive attacks. In this work we propose an on-chip implementation of a reduced set of NIST-SP-800-22 randomness test suite to provide on-line RNG testing for low cost security devices along with runtime monitoring of RNG performance. The on-chip NIST module monitors the effect of dynamic variation of operating condition and time dependent wear-out on RNG circuits. It indicates invasive attacks on RNG and allows the secure system to take protective measures. Six NIST tests are optimized to a hardware design friendly format, but in compliance with the NIST standard. The lightweight implementations reduce complex statistical and arithmetic operations of conventional NIST tests to a series of bit stream count and compare operations. A cycle-to-cycle serial test of incoming bits from RNG eliminates need for additional storage. A partial re-configurable feature is designed to set the pass/fail threshold for each test depending on the system requirements. The on-chip NIST module, although not exhaustive, is an effective layer of validation and security for RNG circuits. The six 128-bit tests implemented in 45nm NCSU PDK have a total synthesized area of ~1926.sq.um for an optimized frequency of 2GHz. The total dynamic power is 3.75mW and leakage power is 10.5μW. At 2Gbps, the NIST module consumes 1.87pJ/bit. The lightweight ultra-low power implementation is scalable for larger input bit samples.","PeriodicalId":6337,"journal":{"name":"2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"23 1","pages":"93-98"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80500306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/HST.2013.6581559
D. Merli, Johann Heyszl, Benedikt Heinz, Dieter Schuster, F. Stumpf, G. Sigl
Among all proposed Physical Unclonable Functions (PUFs), those based on Ring Oscillators (ROs) are a popular solution for ASICs as well as for FPGAs. However, compared to other PUF architectures, oscillators emit electromagnetic (EM) signals over a relatively long run time, which directly reveal their unique frequencies. Previous work by Merli et al. exploited this fact by global EM measurements and proposed a countermeasure for their attack. In this paper, we first demonstrate that it is feasible to measure and locate the EM emission of a single tiny RO consisting of only three inverters, implemented within a single configurable logic block of a Xilinx Spartan-3A. Second, we present a localized EM attack for standard and protected RO PUFs. We practically investigate the proposed side-channel attack on a protected FPGA RO PUF implementation. We show that RO PUFs are prone to localized EM attacks and propose two countermeasures, namely, randomization of RO measurement logic and interleaved placement.
{"title":"Localized electromagnetic analysis of RO PUFs","authors":"D. Merli, Johann Heyszl, Benedikt Heinz, Dieter Schuster, F. Stumpf, G. Sigl","doi":"10.1109/HST.2013.6581559","DOIUrl":"https://doi.org/10.1109/HST.2013.6581559","url":null,"abstract":"Among all proposed Physical Unclonable Functions (PUFs), those based on Ring Oscillators (ROs) are a popular solution for ASICs as well as for FPGAs. However, compared to other PUF architectures, oscillators emit electromagnetic (EM) signals over a relatively long run time, which directly reveal their unique frequencies. Previous work by Merli et al. exploited this fact by global EM measurements and proposed a countermeasure for their attack. In this paper, we first demonstrate that it is feasible to measure and locate the EM emission of a single tiny RO consisting of only three inverters, implemented within a single configurable logic block of a Xilinx Spartan-3A. Second, we present a localized EM attack for standard and protected RO PUFs. We practically investigate the proposed side-channel attack on a protected FPGA RO PUF implementation. We show that RO PUFs are prone to localized EM attacks and propose two countermeasures, namely, randomization of RO measurement logic and interleaved placement.","PeriodicalId":6337,"journal":{"name":"2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"20 3","pages":"19-24"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91491753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/HST.2013.6581558
Mukund Kalyanaraman, M. Orshansky
Many strong silicon physical unclonable functions (PUFs) are known to be vulnerable to machine-learning attacks due to linear separability of the output function. This significantly limits their potential as reliable security primitives. We introduce a novel strong silicon PUF based on the exponential current-voltage behavior in subthreshold region of FET operation which injects strong nonlinearity into the response of the PUF. The PUF, which we term subthreshold current array (SCA) PUF, is implemented as a pair of two-dimensional n × k transistor arrays with all devices subject to stochastic variability operating in subthreshold region. Our PUF is fundamentally different from earlier attempts to inject nonlinearity via digital control techniques, which could also be used with SCA-PUF. Voltages produced by nominally identical arrays are compared to produce a random binary response. SCA-PUF shows excellent security properties. The average inter-class Hamming distance, a measure of uniqueness, is 50.2%. The average intra-class Hamming distance, a measure of response stability, is 4.17%. Crucially, we demonstrate that the introduced PUF is much less vulnerable to modeling attacks. Using machine-learning techniques of support-vector machine with radial basis function kernel and logistic regression for best nonlinear learnability, we observe that “information leakage” (rate of error reduction with learning) is much lower than for delay-based PUFs. Over a wide range of the number of observed challenge-response pairs, the error rate is 3-35X higher than for the delay-based PUF. We also demonstrate an enhanced SCAPUF design utilizing XOR scrambling and show that it has an up to 30X higher error rate compared to the XOR delay-based PUF.
{"title":"Novel strong PUF based on nonlinearity of MOSFET subthreshold operation","authors":"Mukund Kalyanaraman, M. Orshansky","doi":"10.1109/HST.2013.6581558","DOIUrl":"https://doi.org/10.1109/HST.2013.6581558","url":null,"abstract":"Many strong silicon physical unclonable functions (PUFs) are known to be vulnerable to machine-learning attacks due to linear separability of the output function. This significantly limits their potential as reliable security primitives. We introduce a novel strong silicon PUF based on the exponential current-voltage behavior in subthreshold region of FET operation which injects strong nonlinearity into the response of the PUF. The PUF, which we term subthreshold current array (SCA) PUF, is implemented as a pair of two-dimensional n × k transistor arrays with all devices subject to stochastic variability operating in subthreshold region. Our PUF is fundamentally different from earlier attempts to inject nonlinearity via digital control techniques, which could also be used with SCA-PUF. Voltages produced by nominally identical arrays are compared to produce a random binary response. SCA-PUF shows excellent security properties. The average inter-class Hamming distance, a measure of uniqueness, is 50.2%. The average intra-class Hamming distance, a measure of response stability, is 4.17%. Crucially, we demonstrate that the introduced PUF is much less vulnerable to modeling attacks. Using machine-learning techniques of support-vector machine with radial basis function kernel and logistic regression for best nonlinear learnability, we observe that “information leakage” (rate of error reduction with learning) is much lower than for delay-based PUFs. Over a wide range of the number of observed challenge-response pairs, the error rate is 3-35X higher than for the delay-based PUF. We also demonstrate an enhanced SCAPUF design utilizing XOR scrambling and show that it has an up to 30X higher error rate compared to the XOR delay-based PUF.","PeriodicalId":6337,"journal":{"name":"2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"27 1","pages":"13-18"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89370464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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