A 3-V, 1.47-mW, 120-MHz comparator for use in a pipeline ADC

Abstract

A low-voltage and low-power comparator suitable for use in a pipeline analog-to-digital converter is implemented in CMOS 0.8 /spl mu/m technology. The maximum clock frequency with DC inputs is 160 MHz. With a 10 MHz input sine wave at v/sub i+/, DC at v/sub i-/, and a clock frequency of 120 MHz, the measured rise-time, fail-time, delay-time, and power consumption are 1.28 ns, 1.37 ns, 1.60 ns and 1.47 mW, respectively. The optimization issue of the comparator is discussed.