A study of BEOL resistance mismatch in double patterning process

Abstract

Matched circuit components are widely used in logic circuits including resistors, capacitors and transistors. Any variations in those components could cause mismatch in circuit performance. In advanced technology nodes, double patterning (litho/etch/litho/etch) process has been introduced to pattern BEOL metal and via levels. Two patterning steps (litho/etch/litho/etch) with two sets of masks for litho printing and with two independent etch processes, could result in pattern dimension difference which leads to resistance and capacitance (RC) mismatch. In wire or via heavily dominated logic circuits, this RC mismatch may be sensitive to design-matched circuit components. In this paper, we studied resistance mismatch in 14nm BEOL metal level where the double patterning process is used. The mismatch of metal resistance between two locations with same-mask design and two-mask design are studied. The mismatch systematic mean offset and random variability have been discussed. The methodology of determining whether the mismatch is dominated by systematic mean offset or random variability and how to quantify the mismatch variability has been introduced and discussed in this paper.