An efficient seeds selection method for LFSR-based test-per-clock BIST

Abstract

Built-in self-test (BIST) is an effective approach for testing large and complex circuits. When BIST is used, a test pattern generator (TPG), a test response verifier and a BIST controller accompany the circuit under test (CUT) in the chip, creating a self-testable circuit. In this paper we propose a new algorithm for seeds selection in LFSR (linear feedback shift register) based test-per-clock BIST. The proposed algorithm uses the well-known concept of solving systems of linear equations and, based on heuristics, minimizes the number of seeds and test vectors while achieving 100% fault coverage. Experimental results indicate that it compares favorably to the other known techniques.