M. Borgatti, A. Rocchi, Marco Bisio, M. Besana, L. Navoni, P. Rolandi
{"title":"A 64 min single-chip voice recorder/player using embedded 4 bit/cell flash memory","authors":"M. Borgatti, A. Rocchi, Marco Bisio, M. Besana, L. Navoni, P. Rolandi","doi":"10.1109/CICC.2000.852652","DOIUrl":null,"url":null,"abstract":"A system-on-chip prototype implements a full integration of a 64-minute digital voice recorder/player embedding a 4 bit/cell multilevel digital flash memory. A speech coder/decoder (8 to 40 kbps), an MCU and an 8 Mcell/32 Mb multilevel flash memory with fully digital on-chip BIST solution are integrated in a 0.5 /spl mu/m embedded flash technology. The system features a modular architecture allowing full reuse and mix-and-match of its IP building blocks. The chip counts 13M transistors at 225 mm/sup 2/ area.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"31 1","pages":"219-222"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2000.852652","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
A system-on-chip prototype implements a full integration of a 64-minute digital voice recorder/player embedding a 4 bit/cell multilevel digital flash memory. A speech coder/decoder (8 to 40 kbps), an MCU and an 8 Mcell/32 Mb multilevel flash memory with fully digital on-chip BIST solution are integrated in a 0.5 /spl mu/m embedded flash technology. The system features a modular architecture allowing full reuse and mix-and-match of its IP building blocks. The chip counts 13M transistors at 225 mm/sup 2/ area.
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