{"title":"A programmable data-path for MPEG-4 and natural hybrid video coding","authors":"A. Faroqui, V.G. Okobdzija","doi":"10.1109/ACSSC.2000.911274","DOIUrl":null,"url":null,"abstract":"A programmable data-path that supports MPEG standards Synthetic & Natural Hybrid video Coding (SNHC) is presented. It can support a maximum of 16 parallel SIMD integer operations and 2 parallel SIMD floating-point operations. Two new instructions were added in order to increase the execution of 3D graphics and SNHC as well as to speed up IDCT, FFT, and other media signal processing algorithms. These operations are implemented by re-using the hardware without significant increase in area and delay. The datapath has been modeled in Verilog using 0.25u CMOS library and synthesized using Synopsys. All operations are single-cycle running at 200 MHz.","PeriodicalId":10581,"journal":{"name":"Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154)","volume":"49 1","pages":"1675-1678 vol.2"},"PeriodicalIF":0.0000,"publicationDate":"2000-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ACSSC.2000.911274","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
A programmable data-path that supports MPEG standards Synthetic & Natural Hybrid video Coding (SNHC) is presented. It can support a maximum of 16 parallel SIMD integer operations and 2 parallel SIMD floating-point operations. Two new instructions were added in order to increase the execution of 3D graphics and SNHC as well as to speed up IDCT, FFT, and other media signal processing algorithms. These operations are implemented by re-using the hardware without significant increase in area and delay. The datapath has been modeled in Verilog using 0.25u CMOS library and synthesized using Synopsys. All operations are single-cycle running at 200 MHz.
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