Pub Date : 2000-12-01DOI: 10.1109/ACSSC.2000.910763
Zhiqiang Liu, A. Stamoulis, G. Giannakis
Integrated services in wireless networks call for a physical layer which can support multirate transmissions and guarantee symbol recovery at the receiver. Multirate transmissions are necessary for data applications with diverse needs in throughput/delay, whereas symbol recovery leads to quality of service guarantees in terms of bit error rate. We develop a multiuser physical layer framework, which can be used in a wireless integrated services architecture. Capitalizing on space-time coding and block transmissions, we show how space-time transmit antenna diversity can provide transmission rates of arbitrarily fine resolution while guaranteeing symbol recovery irrespective of the FIR wireless channel.
{"title":"Supporting integrated services in wireless networks with space-time block-coded transmissions","authors":"Zhiqiang Liu, A. Stamoulis, G. Giannakis","doi":"10.1109/ACSSC.2000.910763","DOIUrl":"https://doi.org/10.1109/ACSSC.2000.910763","url":null,"abstract":"Integrated services in wireless networks call for a physical layer which can support multirate transmissions and guarantee symbol recovery at the receiver. Multirate transmissions are necessary for data applications with diverse needs in throughput/delay, whereas symbol recovery leads to quality of service guarantees in terms of bit error rate. We develop a multiuser physical layer framework, which can be used in a wireless integrated services architecture. Capitalizing on space-time coding and block transmissions, we show how space-time transmit antenna diversity can provide transmission rates of arbitrarily fine resolution while guaranteeing symbol recovery irrespective of the FIR wireless channel.","PeriodicalId":10581,"journal":{"name":"Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154)","volume":"63 1","pages":"1250-1254 vol.2"},"PeriodicalIF":0.0,"publicationDate":"2000-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88767237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-01DOI: 10.1109/ACSSC.2000.911018
Z. Chi, Zhongfeng Wang, K. Parhi
For high data rate transmission over wireless fading channels, space-time trellis coding techniques can be employed to increase the information capacity of the communication system dramatically. In this paper, we consider the scenario of iterative decoding of concatenated space-time trellis codes and convolutional codes. Extra coding gains in addition to the diversity advantage are shown to be achieved for certain space-time trellis codes transmitted over both quasi-static and fast flat fading channels. A prestudy of related VLSI implementation issues is also presented which includes the finite word-length analysis for serial concatenated space-time trellis turbo decoders and hardware saving strategies.
{"title":"Iterative decoding of space-time trellis codes and related implementation issues","authors":"Z. Chi, Zhongfeng Wang, K. Parhi","doi":"10.1109/ACSSC.2000.911018","DOIUrl":"https://doi.org/10.1109/ACSSC.2000.911018","url":null,"abstract":"For high data rate transmission over wireless fading channels, space-time trellis coding techniques can be employed to increase the information capacity of the communication system dramatically. In this paper, we consider the scenario of iterative decoding of concatenated space-time trellis codes and convolutional codes. Extra coding gains in addition to the diversity advantage are shown to be achieved for certain space-time trellis codes transmitted over both quasi-static and fast flat fading channels. A prestudy of related VLSI implementation issues is also presented which includes the finite word-length analysis for serial concatenated space-time trellis turbo decoders and hardware saving strategies.","PeriodicalId":10581,"journal":{"name":"Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154)","volume":"16 1","pages":"562-566 vol.1"},"PeriodicalIF":0.0,"publicationDate":"2000-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82635925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-01DOI: 10.1109/ACSSC.2000.910666
S. Nelatury, Sathyanarayan S. Rao
The constant modulus (CM) criterion coupled with a gradient search helps in the design of fractionally spaced equalizers. Effective implementation of CM algorithm requires proper choice of the scale factor /spl mu/ called the step size and initialization of equalizer coefficients. Experience reveals that these two determine the convergence rate and final misadjustment. Recently Brown et al. proposed a computationally efficient algorithm, which is a signed error version of CMA. This paper proposes yet another variation of the same and reports faster convergence. The idea is to use variable step size, which increases the convergence rate.
{"title":"A fast constant modulus algorithm for blind equalization","authors":"S. Nelatury, Sathyanarayan S. Rao","doi":"10.1109/ACSSC.2000.910666","DOIUrl":"https://doi.org/10.1109/ACSSC.2000.910666","url":null,"abstract":"The constant modulus (CM) criterion coupled with a gradient search helps in the design of fractionally spaced equalizers. Effective implementation of CM algorithm requires proper choice of the scale factor /spl mu/ called the step size and initialization of equalizer coefficients. Experience reveals that these two determine the convergence rate and final misadjustment. Recently Brown et al. proposed a computationally efficient algorithm, which is a signed error version of CMA. This paper proposes yet another variation of the same and reports faster convergence. The idea is to use variable step size, which increases the convergence rate.","PeriodicalId":10581,"journal":{"name":"Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154)","volume":"52 1","pages":"1010-1013 vol.2"},"PeriodicalIF":0.0,"publicationDate":"2000-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76534354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-01DOI: 10.1109/ACSSC.2000.910652
R. Heath, J. Tellado, S.K. Peroor, A. Paulraj
Interference cancellation or joint detection in cellular systems can be used to improve the quality, capacity, or coverage. Gains may be limited, however, due to the lack of coordination between base stations. This resulting asynchronicity increases channel estimation error and degrades the performance of receivers which mitigate interference. We propose a cellular architecture, using sectored base station antennas, that employs successive time delays to reduce the asynchronicity of interfering transmissions. Training sequence assignments are coordinated among cells to ensure that both signal and interferer are trained. We derive the largest allowable offset correction for both uplink and downlink transmissions according to certain criteria. Examples using ideal cellular layouts are presented along with discussion of application to nonideal terrains.
{"title":"Coordinated training and transmission for improved interference cancellation in a cellular network","authors":"R. Heath, J. Tellado, S.K. Peroor, A. Paulraj","doi":"10.1109/ACSSC.2000.910652","DOIUrl":"https://doi.org/10.1109/ACSSC.2000.910652","url":null,"abstract":"Interference cancellation or joint detection in cellular systems can be used to improve the quality, capacity, or coverage. Gains may be limited, however, due to the lack of coordination between base stations. This resulting asynchronicity increases channel estimation error and degrades the performance of receivers which mitigate interference. We propose a cellular architecture, using sectored base station antennas, that employs successive time delays to reduce the asynchronicity of interfering transmissions. Training sequence assignments are coordinated among cells to ensure that both signal and interferer are trained. We derive the largest allowable offset correction for both uplink and downlink transmissions according to certain criteria. Examples using ideal cellular layouts are presented along with discussion of application to nonideal terrains.","PeriodicalId":10581,"journal":{"name":"Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154)","volume":"10 1","pages":"939-945 vol.2"},"PeriodicalIF":0.0,"publicationDate":"2000-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84650397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-01DOI: 10.1109/ACSSC.2000.911279
Lei Wang, N. Shanbhag
This paper presents a low-power digital filtering technique derived via algorithmic noise-tolerance (ANT). The proposed technique achieves substantial energy savings via voltage overscaling (VOS), where the supply voltage is scaled beyond the minimum (referred to as V/sub dd-crit/) necessary for correct operation. The resulting performance degradation is compensated for via an adaptive error-cancellation (AEC) algorithm. In particular, we employ an energy optimum AEC to optimize the energy-performance trade-off and reduce the overhead due to ANT. It is shown that the proposed AEC technique is well-suited for designing low-power broadband signal processing and communication systems. Up to 71% energy savings over optimally voltage-scaled conventional systems can be obtained in the context of frequency-division multiplexed (FDM) communications without incurring any performance loss.
{"title":"Adaptive error-cancellation for low-power digital filtering","authors":"Lei Wang, N. Shanbhag","doi":"10.1109/ACSSC.2000.911279","DOIUrl":"https://doi.org/10.1109/ACSSC.2000.911279","url":null,"abstract":"This paper presents a low-power digital filtering technique derived via algorithmic noise-tolerance (ANT). The proposed technique achieves substantial energy savings via voltage overscaling (VOS), where the supply voltage is scaled beyond the minimum (referred to as V/sub dd-crit/) necessary for correct operation. The resulting performance degradation is compensated for via an adaptive error-cancellation (AEC) algorithm. In particular, we employ an energy optimum AEC to optimize the energy-performance trade-off and reduce the overhead due to ANT. It is shown that the proposed AEC technique is well-suited for designing low-power broadband signal processing and communication systems. Up to 71% energy savings over optimally voltage-scaled conventional systems can be obtained in the context of frequency-division multiplexed (FDM) communications without incurring any performance loss.","PeriodicalId":10581,"journal":{"name":"Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154)","volume":"7 1","pages":"1702-1706 vol.2"},"PeriodicalIF":0.0,"publicationDate":"2000-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84179232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-01DOI: 10.1109/ACSSC.2000.911272
S. Banerjee, H. Sheikh, L. John, B. Evans, A. Bovik
A Very Long Instruction Word (VLIW) processor and a superscalar processor can execute multiple instructions simultaneously. A VLIW processor depends on the compiler and programmer to find the parallelism in the instructions, whereas a superscaler processor determines the parallelism at runtime. This paper compares TI TMS320C6700 VLIW digital signal processor (DSP) and SimpleScalar superscalar implementations of a baseline 11.263 video encoder in C. With level two C compiler optimization, a one-way issue superscalar processor is 7.5 times faster than the VLIW DSP for the same processor clock speed. The superscalar speedup from one-way to four-way issue is 2.88:1, and from four-way to 256-way issue is 2.43:1. To reduce the execution time on the C6700, we write assembly routines for sum-of-absolute-difference, interpolation, and reconstruction, and place frequently used code and data into on-chip memory. We use TI's discrete cosine transform assembly routines. The hand optimized VLIW DSP implementation is 61/spl times/ faster than the C version compiled with level two optimization. Most of the improvement was due to the efficient placement of data and programs in memory. The hand optimized VLIW implementation is 14% faster than a 256-way superscalar implementation without hand optimizations.
{"title":"VLIW DSP vs. superscalar implementation of a baseline 11.263 video encoder","authors":"S. Banerjee, H. Sheikh, L. John, B. Evans, A. Bovik","doi":"10.1109/ACSSC.2000.911272","DOIUrl":"https://doi.org/10.1109/ACSSC.2000.911272","url":null,"abstract":"A Very Long Instruction Word (VLIW) processor and a superscalar processor can execute multiple instructions simultaneously. A VLIW processor depends on the compiler and programmer to find the parallelism in the instructions, whereas a superscaler processor determines the parallelism at runtime. This paper compares TI TMS320C6700 VLIW digital signal processor (DSP) and SimpleScalar superscalar implementations of a baseline 11.263 video encoder in C. With level two C compiler optimization, a one-way issue superscalar processor is 7.5 times faster than the VLIW DSP for the same processor clock speed. The superscalar speedup from one-way to four-way issue is 2.88:1, and from four-way to 256-way issue is 2.43:1. To reduce the execution time on the C6700, we write assembly routines for sum-of-absolute-difference, interpolation, and reconstruction, and place frequently used code and data into on-chip memory. We use TI's discrete cosine transform assembly routines. The hand optimized VLIW DSP implementation is 61/spl times/ faster than the C version compiled with level two optimization. Most of the improvement was due to the efficient placement of data and programs in memory. The hand optimized VLIW implementation is 14% faster than a 256-way superscalar implementation without hand optimizations.","PeriodicalId":10581,"journal":{"name":"Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154)","volume":"92 1","pages":"1665-1669 vol.2"},"PeriodicalIF":0.0,"publicationDate":"2000-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82683103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-01DOI: 10.1109/ACSSC.2000.910976
Kuei-Chiang Lai, J. Shynk
In this paper we describe an adaptive algorithm for separating fetal and maternal heart beats from data containing both fetal and maternal QRS complexes. The algorithm classifies the combined heart-rate data as a series of fetal maternal, and noise events using a technique of template matching. Peak detection is first employed to locate the potential fetal and maternal QRS complexes (referred to as candidate events). Fetal and maternal templates are generated automatically from the candidate events in the initialization period, and are used to classify the remaining candidate events based on certain similarity criteria. Once the fetal and maternal complexes are successfully detected and separated, a counting mechanism can be utilized to derive the corresponding heart rates. Computer simulations using real data demonstrate the effectiveness of the algorithm.
{"title":"A signal separation algorithm for fetal heart-rate estimation","authors":"Kuei-Chiang Lai, J. Shynk","doi":"10.1109/ACSSC.2000.910976","DOIUrl":"https://doi.org/10.1109/ACSSC.2000.910976","url":null,"abstract":"In this paper we describe an adaptive algorithm for separating fetal and maternal heart beats from data containing both fetal and maternal QRS complexes. The algorithm classifies the combined heart-rate data as a series of fetal maternal, and noise events using a technique of template matching. Peak detection is first employed to locate the potential fetal and maternal QRS complexes (referred to as candidate events). Fetal and maternal templates are generated automatically from the candidate events in the initialization period, and are used to classify the remaining candidate events based on certain similarity criteria. Once the fetal and maternal complexes are successfully detected and separated, a counting mechanism can be utilized to derive the corresponding heart rates. Computer simulations using real data demonstrate the effectiveness of the algorithm.","PeriodicalId":10581,"journal":{"name":"Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154)","volume":"33 1","pages":"348-351 vol.1"},"PeriodicalIF":0.0,"publicationDate":"2000-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80842503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-01DOI: 10.1109/ACSSC.2000.910944
M. Kawada, M. Ikehara
A large class of lapped biorthogonal transforms using lifting steps (LLBT) is presented. The transform coefficients are parametarized as a basic matrix and a series of lifting steps, providing fast, efficient in-place computation of them. Our main motivation of the new transform is its application in image coding. The LLBT has several long overlapped basis functions of the synthesis bank for representing smooth signals to avoid annoying blocking artifacts. The bases of the synthesis bank covering high-frequency bands are constrained to be short to reduce ringing artifacts. Moreover, the analysis bandpass filters provide better stopband attenuation. Comparing to the popular 8/spl times/8 DCT, the LLBT only requires several more additions and shifting operations. However, image coding examples show that the LLBT is far superior to the DCT and 8/spl times/16 LOT in both objective and subjective coding performance.
{"title":"Generalized lapped biorthogonal transforms using lifting steps","authors":"M. Kawada, M. Ikehara","doi":"10.1109/ACSSC.2000.910944","DOIUrl":"https://doi.org/10.1109/ACSSC.2000.910944","url":null,"abstract":"A large class of lapped biorthogonal transforms using lifting steps (LLBT) is presented. The transform coefficients are parametarized as a basic matrix and a series of lifting steps, providing fast, efficient in-place computation of them. Our main motivation of the new transform is its application in image coding. The LLBT has several long overlapped basis functions of the synthesis bank for representing smooth signals to avoid annoying blocking artifacts. The bases of the synthesis bank covering high-frequency bands are constrained to be short to reduce ringing artifacts. Moreover, the analysis bandpass filters provide better stopband attenuation. Comparing to the popular 8/spl times/8 DCT, the LLBT only requires several more additions and shifting operations. However, image coding examples show that the LLBT is far superior to the DCT and 8/spl times/16 LOT in both objective and subjective coding performance.","PeriodicalId":10581,"journal":{"name":"Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154)","volume":"66 1","pages":"197-201 vol.1"},"PeriodicalIF":0.0,"publicationDate":"2000-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72786652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-01DOI: 10.1109/ACSSC.2000.911250
Yan Xin, Zhengdao Wang, G. Giannakis
In this paper, we analyze the performance of multiple-transmit/receive antenna systems with linear precoders. From the performance of these systems, we deduce design rules for linear precoders. Following the design rules, we prove the existence and derive linear unitary precoders achieving maximum diversity gain. Compared with existing real precoders, the novel unitary precoders offer the potential of larger coding gains. Simulations illustrate that the unitary precoders can achieve more than 1 dB coding gain over real precoders while they perform comparably to repeated transmissions, that consume larger amounts of bandwidth when two or three transmit antennas are utilized.
{"title":"Linear unitary precoders for maximum diversity gains with multiple transmit and receive antennas","authors":"Yan Xin, Zhengdao Wang, G. Giannakis","doi":"10.1109/ACSSC.2000.911250","DOIUrl":"https://doi.org/10.1109/ACSSC.2000.911250","url":null,"abstract":"In this paper, we analyze the performance of multiple-transmit/receive antenna systems with linear precoders. From the performance of these systems, we deduce design rules for linear precoders. Following the design rules, we prove the existence and derive linear unitary precoders achieving maximum diversity gain. Compared with existing real precoders, the novel unitary precoders offer the potential of larger coding gains. Simulations illustrate that the unitary precoders can achieve more than 1 dB coding gain over real precoders while they perform comparably to repeated transmissions, that consume larger amounts of bandwidth when two or three transmit antennas are utilized.","PeriodicalId":10581,"journal":{"name":"Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154)","volume":"26 1","pages":"1553-1557 vol.2"},"PeriodicalIF":0.0,"publicationDate":"2000-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73942332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-01DOI: 10.1109/ACSSC.2000.910655
R. Cagley, Kuei-Chiang Lai, J. Shynk
Maximum likelihood (ML) decision rules, such as that presented by Gutierrez, Lee and Mandyam (see. Proc. IEEE 49th Vehicular Technology Conf., Houston, TX, p.417-21, 1999), can be used for rate determination in an IS-95 system to reduce the complexity of the Viterbi decoder. We extend this previous work by determining whether it is beneficial to use rate determination for the successive interference canceller (SIC) in an IS-95 downlink receiver. Assuming certain conditions are met regarding the signal-to-noise ratio (SNR) and the number of received symbols used for rate determination, employing knowledge of bit repetition can decrease the bit error rare (BER) for the corresponding Walsh channels. To further increase the effectiveness of interference cancellation, soft decision decoding can be used instead of a conventional hard decision device. The devices considered here are similar to those of Frey and Reinhardt (see Proc. IEEE 47th Vehicular Technology Conf., Phoenix, AZ, p.155-159, 1997), but they use the knowledge that there can be repeated bits in the IS-95 downlink.
最大似然(ML)决策规则，如Gutierrez, Lee和Mandyam提出的(见。Proc. IEEE第49届车辆技术会议，休斯顿，德克萨斯州，p.417- 21,1999)，可用于IS-95系统的速率确定，以降低Viterbi解码器的复杂性。我们通过确定is -95下行链路接收器中连续干扰消除器(SIC)的使用率确定是否有益来扩展先前的工作。假设信噪比(SNR)和用于确定速率的接收符号数满足一定条件，利用位重复的知识可以降低相应Walsh信道的误码率(BER)。为了进一步提高干扰消除的有效性，可以采用软判决译码代替传统的硬判决译码。这里考虑的设备类似于Frey和Reinhardt的设备(参见Proc. IEEE第47届车辆技术会议，Phoenix, AZ, p.155-159, 1997)，但他们使用了IS-95下行链路中可以重复比特的知识。
{"title":"Performance of ML rate determination for an IS-95 downlink SIC receiver","authors":"R. Cagley, Kuei-Chiang Lai, J. Shynk","doi":"10.1109/ACSSC.2000.910655","DOIUrl":"https://doi.org/10.1109/ACSSC.2000.910655","url":null,"abstract":"Maximum likelihood (ML) decision rules, such as that presented by Gutierrez, Lee and Mandyam (see. Proc. IEEE 49th Vehicular Technology Conf., Houston, TX, p.417-21, 1999), can be used for rate determination in an IS-95 system to reduce the complexity of the Viterbi decoder. We extend this previous work by determining whether it is beneficial to use rate determination for the successive interference canceller (SIC) in an IS-95 downlink receiver. Assuming certain conditions are met regarding the signal-to-noise ratio (SNR) and the number of received symbols used for rate determination, employing knowledge of bit repetition can decrease the bit error rare (BER) for the corresponding Walsh channels. To further increase the effectiveness of interference cancellation, soft decision decoding can be used instead of a conventional hard decision device. The devices considered here are similar to those of Frey and Reinhardt (see Proc. IEEE 47th Vehicular Technology Conf., Phoenix, AZ, p.155-159, 1997), but they use the knowledge that there can be repeated bits in the IS-95 downlink.","PeriodicalId":10581,"journal":{"name":"Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154)","volume":"142 1","pages":"956-959 vol.2"},"PeriodicalIF":0.0,"publicationDate":"2000-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81747652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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