Energy-efficient hybrid adder design by using inexact lower bits adder

Sunghyun Kim, Youngmin Kim
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引用次数: 14

Abstract

Approximation in the adder logic is a promising solution for energy-efficient designs in various applications. In this study, new hybrid adder design, which consists of an accurate adder for higher bits and proposed approximate adders for lower bits, is investigated. The XOR-based inexact adder is modified to be used in the approximation part. Simulation results of 16-bits adders show that error rates can be reduced significantly by the proposed hybrid adder compared to other approximation adders with smaller number of transistors than an accurate adder.
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采用非精确低位加法器的节能混合加法器设计
在各种应用中,加法器逻辑中的近似是一种很有前途的节能设计解决方案。本文研究了一种新的混合加法器设计,该加法器由高位精确加法器和低位近似加法器组成。对基于xor的不精确加法器进行了改进,用于逼近部分。对16位加法器的仿真结果表明,与晶体管数量少于精确加法器的近似加法器相比,混合加法器可以显著降低误码率。
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