Tool flow for automatic generation of architectures and test-cases to enable the evaluation of CGRAs in the context of HPC applications

Abstract

The toolflow presented in this demo was created to generate CGRA overlay architectures from either algorithm definitions (mainly for evaluation) or from a simple definition format. The output of the toolchain is always the complete definition of the hardware in VHDL and supplemental files providing information regarding the configuration and the interfaces of the created hardware. In the demo, we show the complete process from the selection of an algorithm over the creation of the hardware definition and the generation of the HDL-files to the implemented FPGA design in the Xilinx Vivado software. The main reason for the implementation of the presented tools is the creation of real-world applications for evaluating dynamic-partial reconfiguration in the context of compute intensive tasks. The integration of reconfigurability into the designs is to be done either semi-automatically using the Xilinx tools or automatically using the TLUT/TCON-toolflow proposed by Ghent-University.