A Reconfigurable 28/56 Gb/s PAM4/NRZ Dual-mode SerDes with Hardware-reuse

Abstract

With the explosive growth of data rate demand, four-level pulse amplitude modulation (PAM4) SerDes standards are emerging, while binary non-return-to-zero (NRZ) standards still take the market. This paper proposes a novel dual-mode architecture designed for SerDes application data rate of up to 56 Gb/s with PAM4 modulation, and compatible to the legacy 28 Gb/s standards with NRZ modulation scheme. Attractively, with minor modification, the same hardware to send PAM4 signal can be used to implement a 28 Gb/s NRZ transmitter with 4-tap forward-feedback equalization (FFE), and meanwhile the PAM4 receiver can be easily reconfigured as a half-rate NRZ receiver with 1-tap loop-unrolled decision-feedback equalization (DFE). In addition, a digital duty-cycle correction (DCC) loop ensures the duty-cycle distortion (DCD) jitter introduced by half-rate transmitter architecture being less than 0.01UI in NRZ mode. The architecture is verified in 22nm CMOS FDSOI technology, and the simulation results across lossy channel show that the serial link transceiver can transmit 28/56 Gb/s with the eye opening of 400 mVpp in NRZ mode, and 150 mVpp in PAM4 mode in 1.2 V supply.