Soroush Rasti-Boroujeni, A. Wyrzykowska, M. Mazaheri, A. Palizban, S. Ituah, A. El-Gouhary, Guoyan Chen, H. Gharaei-Garakani, M. Nezhad-Ahmadi, S. Safavi-Naeini
{"title":"A Power Efficient BiCMOS Ka-Band Transmitter Front-End for SATCOM Phased-Arrays","authors":"Soroush Rasti-Boroujeni, A. Wyrzykowska, M. Mazaheri, A. Palizban, S. Ituah, A. El-Gouhary, Guoyan Chen, H. Gharaei-Garakani, M. Nezhad-Ahmadi, S. Safavi-Naeini","doi":"10.1109/IMS30576.2020.9223834","DOIUrl":null,"url":null,"abstract":"A high efficiency 27–30 GHz 130nm BiCMOS transmitter front-end MMIC for mobile satellite communication phased-array is presented. The implemented chip consists of a gain control block with 15 dB gain variation, a 400 degree phase shifter and a high efficiency two stage power amplifier. The chip has a measured transducer gain of 23 dB and power consumption of 45 mW at $P_{1dB}$ of 10.8 dBm. The power added efficiency (PAE) of 26.7% is measured for the entire channel at $P_{1dB}$. An error vector magnitude (EVM) of -29 dB at $P_{out,avg}$ of 5.7 dBm and $PAE_{avg}$ of 12% is measured for a 400 MHz bandwidth 64-QAM (1.8 Gbps) modulated signal. The overall size of the chip is 2.1×0.8 mm2.","PeriodicalId":6784,"journal":{"name":"2020 IEEE/MTT-S International Microwave Symposium (IMS)","volume":"1 1","pages":"1223-1226"},"PeriodicalIF":0.0000,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE/MTT-S International Microwave Symposium (IMS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMS30576.2020.9223834","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract
A high efficiency 27–30 GHz 130nm BiCMOS transmitter front-end MMIC for mobile satellite communication phased-array is presented. The implemented chip consists of a gain control block with 15 dB gain variation, a 400 degree phase shifter and a high efficiency two stage power amplifier. The chip has a measured transducer gain of 23 dB and power consumption of 45 mW at $P_{1dB}$ of 10.8 dBm. The power added efficiency (PAE) of 26.7% is measured for the entire channel at $P_{1dB}$. An error vector magnitude (EVM) of -29 dB at $P_{out,avg}$ of 5.7 dBm and $PAE_{avg}$ of 12% is measured for a 400 MHz bandwidth 64-QAM (1.8 Gbps) modulated signal. The overall size of the chip is 2.1×0.8 mm2.
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