Cu pillar exposed-die molded FCCSP for mobile devices

Abstract

Due to more build-in functions and smaller form factor requirements, mobile devices are required to have better thermal dissipation performance and thinner IC package profile. In this study, a new package which combines Cu pillar bumps with IC backside exposed-die properties is introduced. Compared with solder bumps, Cu pillar bumps can effectively increase substrate circuit layout density and then reduce substrate layers or shrink package sizes to achieve cost down benefit. Also, compared with traditional over-mold FCCSP, IC backside exposed-die molded FCCSP can effectively eliminate roughly 100μm of package height to achieve thin package requirement. Moreover, exposed-die also can provide better thermal dissipation performance, i.e., Theta JC, when it is attached to an external heat spreader/sink or EMC shielding case. However, compared with solder bumps, Cu pillar bumps (with higher modulus property) will introduce higher mechanical stress to ELK layer and may cause potential ELK cracking issue. Also, compared with traditional over mold package, exposed-die will introduce serious package warpage issue and may cause potential low SMT yield problem. Therefore, the solutions to reduce the mechanical stress from Cu pillar bump to the ELK layer and improve the warpage for exposed-die have aroused lots of attention in semiconductor industry, especially on FCCSP and PoP (Package on Package) recently. In this study, lots of mechanical simulation models and DOE studies used to address how to effectively reduce ELK stress such as adding PI, changing bump shapes, change to DUAL UBM, or adding one RDL layer. Moreover, how substrate or molding compound material selected (such as CTE or Tg adjustment) can effectively reduce package warpage and then eventually improve FCCSP SMT and stacking PoP yields are addressed as well