Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons, J. Emer, Matthew R. Fojtik, Alicia Klinefelter, Michael Pellauer, N. Pinckney, Y. Shao, S. Srinath, Christopher Torng, S. Xi, Yanqing Zhang, B. Zimmer
{"title":"INVITED: A Modular Digital VLSI Flow for High-Productivity SoC Design","authors":"Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons, J. Emer, Matthew R. Fojtik, Alicia Klinefelter, Michael Pellauer, N. Pinckney, Y. Shao, S. Srinath, Christopher Torng, S. Xi, Yanqing Zhang, B. Zimmer","doi":"10.1145/3195970.3199846","DOIUrl":null,"url":null,"abstract":"A high-productivity digital VLSI flow for designing complex SoCs is presented. The flow includes high-level synthesis tools, an object-oriented library of synthesizable SystemC and C++ components, and a modular VLSI physical design approach based on fine-grained globally asynchronous locally synchronous (GALS) clocking. The flow was demonstrated on a 16nm FinFET testchip targeting machine learning and computer vision.","PeriodicalId":6491,"journal":{"name":"2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)","volume":"43 1","pages":"1-6"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"50","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/3195970.3199846","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 50
Abstract
A high-productivity digital VLSI flow for designing complex SoCs is presented. The flow includes high-level synthesis tools, an object-oriented library of synthesizable SystemC and C++ components, and a modular VLSI physical design approach based on fine-grained globally asynchronous locally synchronous (GALS) clocking. The flow was demonstrated on a 16nm FinFET testchip targeting machine learning and computer vision.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
