{"title":"Effect of technology scaling on digital CMOS logic styles","authors":"M. Allam, M. Anis, M. Elmasry","doi":"10.1109/CICC.2000.852695","DOIUrl":null,"url":null,"abstract":"In this paper, the main challenges of technology scaling are reviewed in depth. Five popular logic families, namely, conventional CMOS, CPL, Domino, DCVS and MCML are represented highlighting their advantages and drawbacks. The behavior of each logic style in deep submicron technologies is analyzed and predicted for future generations. To verify the qualitative analysis, simulations were performed on the basic logic gates, full adder and a 16-bit carry look ahead adder. The circuits were implemented in 0.8, 0.6, 0.35 and 0.25 /spl mu/m CMOS technologies.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"32 1","pages":"401-408"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2000.852695","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12
Abstract
In this paper, the main challenges of technology scaling are reviewed in depth. Five popular logic families, namely, conventional CMOS, CPL, Domino, DCVS and MCML are represented highlighting their advantages and drawbacks. The behavior of each logic style in deep submicron technologies is analyzed and predicted for future generations. To verify the qualitative analysis, simulations were performed on the basic logic gates, full adder and a 16-bit carry look ahead adder. The circuits were implemented in 0.8, 0.6, 0.35 and 0.25 /spl mu/m CMOS technologies.
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