A digital low-dropout-regulator with steady-state load current (SLC) estimator and dynamic gain scaling (DGS) control

Jian-He Lin, Wen-Jie Tsou, Ke-Horng Chen, Chinder Wey, Ying-Hsi Lin, Jian-Ru Lin, Lsung-Yen Lsai
{"title":"A digital low-dropout-regulator with steady-state load current (SLC) estimator and dynamic gain scaling (DGS) control","authors":"Jian-He Lin, Wen-Jie Tsou, Ke-Horng Chen, Chinder Wey, Ying-Hsi Lin, Jian-Ru Lin, Lsung-Yen Lsai","doi":"10.1109/APCCAS.2016.7803889","DOIUrl":null,"url":null,"abstract":"Conventional digital low dropout (D-LDO) regulator usually suffers from the drawback of long settling time during transient response due to the usage of shift register architecture. In this paper, the proposed D-LDO regulator can observe the output voltage variations during load transient time to predict the load current for fast transient response. Near optimum turn-on power MOSFET in steady state can be derived by the proposed steady-state load current (SLC) estimator while the dynamic gain scaling (DGS) technique can improve transient response and avoid limiting cycle oscillation (LCO) problem. Test chip was designed in 0.18μm CMOS process. Simulation results showed the transient response time can be reduced by 88% from 920ns to 115ns.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.2016.7803889","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5

Abstract

Conventional digital low dropout (D-LDO) regulator usually suffers from the drawback of long settling time during transient response due to the usage of shift register architecture. In this paper, the proposed D-LDO regulator can observe the output voltage variations during load transient time to predict the load current for fast transient response. Near optimum turn-on power MOSFET in steady state can be derived by the proposed steady-state load current (SLC) estimator while the dynamic gain scaling (DGS) technique can improve transient response and avoid limiting cycle oscillation (LCO) problem. Test chip was designed in 0.18μm CMOS process. Simulation results showed the transient response time can be reduced by 88% from 920ns to 115ns.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
具有稳态负载电流(SLC)估计器和动态增益缩放(DGS)控制的数字低差调节器
传统的数字低差(D-LDO)稳压器由于采用移位寄存器结构,在瞬态响应过程中存在稳定时间长的缺点。本文提出的D-LDO稳压器可以观察负载暂态期间的输出电压变化,从而预测负载电流,实现快速的暂态响应。利用所提出的稳态负载电流(SLC)估计器可以得到稳态时的近最优导通功率,而动态增益缩放(DGS)技术可以改善瞬态响应并避免限环振荡(LCO)问题。测试芯片采用0.18μm CMOS工艺设计。仿真结果表明,瞬态响应时间由920ns缩短至115ns,缩短了88%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
IoT and Blockchain: Technologies, Challenges, and Applications Teaching Practice Platform and Innovation Course Construction for Postgraduate Majoring in Electronics Information FPGA implementation of edge detection for Sobel operator in eight directions Analog integrated audio frequency synthesizer Analysis of non-ideal effects and electrochemical impedance spectroscopy of arrayed flexible NiO-based pH sensor
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1