FLOVA: A four-issue VLIW geometry processor with SIMD instructions and lighting acceleration unit

S. Nam, Byoung-Woon Kim, Y. Im, Young-Su Kwon, Jun-Hee Lee, Young-Wook Cheon, Sung-Jae Byun, Dae-Hyun Lee, C. Kyung
{"title":"FLOVA: A four-issue VLIW geometry processor with SIMD instructions and lighting acceleration unit","authors":"S. Nam, Byoung-Woon Kim, Y. Im, Young-Su Kwon, Jun-Hee Lee, Young-Wook Cheon, Sung-Jae Byun, Dae-Hyun Lee, C. Kyung","doi":"10.1109/CICC.2000.852728","DOIUrl":null,"url":null,"abstract":"This paper describes a VLIW (very long instruction word) geometry processor called FLOVA (FLOating-Point VLIW Architecture) which was developed to accelerate the geometry stage of 3D graphics. FLOVA executes four instructions in one cycle and supports 136 instructions including 35 SIMD (single instruction multiple data) instructions to accelerate the geometry stage. Special features to accelerate transformation and lighting operations in 3D graphics geometry stage are described. FLOVA can calculate the power value of two floating-point numbers in only four clock cycles with a negligible loss of accuracy, compared to over 150 clock cycles in other processors.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"30 1","pages":"551-554"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2000.852728","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

This paper describes a VLIW (very long instruction word) geometry processor called FLOVA (FLOating-Point VLIW Architecture) which was developed to accelerate the geometry stage of 3D graphics. FLOVA executes four instructions in one cycle and supports 136 instructions including 35 SIMD (single instruction multiple data) instructions to accelerate the geometry stage. Special features to accelerate transformation and lighting operations in 3D graphics geometry stage are described. FLOVA can calculate the power value of two floating-point numbers in only four clock cycles with a negligible loss of accuracy, compared to over 150 clock cycles in other processors.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
FLOVA:一个带有SIMD指令和光照加速单元的四问题VLIW几何处理器
本文介绍了一种名为FLOVA (FLOating-Point VLIW Architecture)的VLIW (very long instruction word)几何处理器,它是为加速三维图形的几何阶段而开发的。FLOVA在一个周期内执行4条指令,支持136条指令,其中包括35条SIMD(单指令多数据)指令,以加速几何阶段。描述了在3D图形几何阶段加速转换和照明操作的特殊功能。FLOVA可以在四个时钟周期内计算两个浮点数的功率值,精度损失可以忽略不计,而其他处理器则需要超过150个时钟周期。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter Physical processes of phase noise in differential LC oscillators Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration Complete noise analysis for CMOS switching mixers via stochastic differential equations A 6-bit 1 GHz acquisition speed CMOS flash ADC with digital error correction
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1