Systolic architectures for parallel Fourier transform

Abstract

Novel systolic architectures are proposed for the computation of the Fourier transform based on the generation of the coefficients of the transform during the computation. These architectures require fewer input/output pins on the chip. The novel architectures are also extremely modular and cascadable, and thus are amenable to efficient VLSI implementation. The VLSI complexity of the architectures is compared with that of existing parallel architectures.<>