Sooeun Lee, Jaeyoung Seo, Kyunghyun Lim, Jaehyun Ko, J. Sim, Hong-June Park, Byungsub Kim
{"title":"A 7.8Gb/s/pin 1.96pJ/b compact single-ended TRX and CDR with phase-difference modulation for highly reflective memory interfaces","authors":"Sooeun Lee, Jaeyoung Seo, Kyunghyun Lim, Jaehyun Ko, J. Sim, Hong-June Park, Byungsub Kim","doi":"10.1109/ISSCC.2018.8310289","DOIUrl":null,"url":null,"abstract":"Compact transceivers (TRXs) for highly reflective (HR) interconnects are strongly demanded by the memory industry. Although discontinuous reflective channels like multi-drop DRAM interfaces are less suitable for high data rates than continuous point-to-point channels, their great advantages in high capacity, high throughput, and low latency attract the market [1-3]. However, compact TRXs for low-loss HR channels are more challenging than for high-loss low-reflection (LR) channels. Although the long-tail ISI of a high-loss LR channel can be cost-efficiently canceled by an FFE with a few taps or a DFE with IIR feedback (DFE-IIR) [4], the irregular ISI of a low-loss HR channel requires many DFE taps [2], demanding unacceptably large hardware cost and power dissipation. As an alternative solution, a multi-tone (MT) TRX was proposed to avoid a notch of the frequency response [3], but it is also very costly for HR channels with many notches. This paper proposes a 7.8Gb/s/pin compact single-ended (SE) TRX with simple clock data recovery (CDR) using phase-difference modulation (PDM) for HR memory interfaces. For reliable operation of the TRX/CDR, a phase-difference amplifier (PDA) is also proposed to satisfy its stringent timing requirement.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"105 1","pages":"272-274"},"PeriodicalIF":0.0000,"publicationDate":"2018-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2018.8310289","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
Compact transceivers (TRXs) for highly reflective (HR) interconnects are strongly demanded by the memory industry. Although discontinuous reflective channels like multi-drop DRAM interfaces are less suitable for high data rates than continuous point-to-point channels, their great advantages in high capacity, high throughput, and low latency attract the market [1-3]. However, compact TRXs for low-loss HR channels are more challenging than for high-loss low-reflection (LR) channels. Although the long-tail ISI of a high-loss LR channel can be cost-efficiently canceled by an FFE with a few taps or a DFE with IIR feedback (DFE-IIR) [4], the irregular ISI of a low-loss HR channel requires many DFE taps [2], demanding unacceptably large hardware cost and power dissipation. As an alternative solution, a multi-tone (MT) TRX was proposed to avoid a notch of the frequency response [3], but it is also very costly for HR channels with many notches. This paper proposes a 7.8Gb/s/pin compact single-ended (SE) TRX with simple clock data recovery (CDR) using phase-difference modulation (PDM) for HR memory interfaces. For reliable operation of the TRX/CDR, a phase-difference amplifier (PDA) is also proposed to satisfy its stringent timing requirement.