A highly reconfigurable 65nm CMOS RF-to-bits transceiver for full-band multicarrier TDD/FDD 2G/3G/4G/5G macro basestations

Abstract

This paper presents a 65nm 2-TX, 2-RX RF-to-bits basestation transceiver with 200MHz large-signal BW and 450MHz DPD synthesis/observation BW, and LO frequencies from 400MHz to 6GHz. For FDD operation the TRX supports a low-IF mode that meets the dynamic range requirements of GSM basestations. It provides full-band multicarrier (MC) operation in all TDD/FDD 3GPP bands for 2G/3G/4G/5G radios. The SoC includes an 8×16Gb/s SERDES interface, two receivers, two transmitters, and a digital pre-distortion (DPD) feedback RX (FBRX) (Fig. 9.3.1). The FBRX employs a “stitching” system that combines the outputs of both RX basebands to provide 450MHz of observation BW. Three PLLs provide the digital/converter/SERDES clocks, a calibration LO, and an RF LO that meets GSM TX phase-noise requirements. Digital interpolation, decimation, AGC, TX Power control, and calibrations are managed by an integrated ARM Cortex M3. Internal calibration timing is adaptable to support 3G/4G/5G subframe timing requirements. The SoC is a single-chip solution for TDD, and a two-chip set for FDD. GSM requires an external Lo for the RX. Power dissipation in the maximum BW mode (2T/2R/1FBRX, 450/200/450MHz, 0dB RF attenuation, 50% TX/RX duty cycle for TDD) is 4.1W for TDD and 6.6W for FDD.