Impact of stress-induced heating on PLR and WLR HCI testing

Abstract

Hot carrier (HCI) is typical reliability test in qualifying new MOSFET device specified in JEDEC JP001 [1]. The tests are normally conducted on wafer level (WLR) using a manual probe station or automatic tester with probe card. Packaged level reliability (PLR) test system is used as well to test the MOSFET device in parallel. PLR allows higher number of samples (device under test, DUT) to be tested within a much shorter time, even applying longer stress time. The electrical connection through package units, sockets, and test boards is expected more stable than probing contact between probe pads and probe needle tips. Hence, more consistent degradation among DUT-to-DUT and accurate lifetime extrapolation can be achieved. The correlation between WLR and PLR was studied for MOSFET devices with 3.3 volt operating condition and also 12V LDMOS device. The PLR showed higher HCI degradation compared to WLR for 12V LDMOS device, whereas comparable for MOSFET. This was very low level of device self-heating effect on LDMOS from characteristic curves. However, the heat dissipation from ceramic packages took time compared to large silicon wafer on probe chuck. The stress-induced heating impact on LDMOS is discussed in this paper.