Electrical Performance of High Density 10 µm Diameter 20 µm Pitch Cu-Pillar with Chip to Wafer Assembly

Abstract

Microbump-based interconnects with 20 µm pitch have been fabricated on 300 mm wafers using industrial tools. Good processes control enables to get narrow standard deviations for the microbumps height (0.2 µm) and diameter (0.4 µm). Assembly was studied with chip to wafer (CtW) test vehicles by either mass reflow (MR) or thermo-compression (TC) with or without non-conductive paste (NCP). MR and TC processes result in suitable CtW alignments without significant defects at bonding interface. TC NCP assembly suffers from larger misalignment and underfill entrapment, reducing top to bottom bonding section. Consequently, unit electrical resistance is lower for MR and TC processes with ~25 m ascribed to pure vertical link, than for TC NCP process exhibiting ~50 m vertical link with larger standard deviation (15 m versus 2 m). Intermetallic compounds have been studied and Ni3Sn4 proves to be the main contributor for electrical resistance in our configuration where SnAg is sandwiched between 2 Ni layers. Electrical yield measured on daisy chains is very good (close to or higher than 90%) for MR or TC, even on more than 20,000 interconnects. For TC NCP, electrical yield remains to be improved, particularly on large daisy chains. Finally, an original electrical test has been designed and successfully implemented to characterize top to bottom misalignment. These results are promising for future high performance computing products that would require 20 µm pitch microbumps.