A multiprocessor System On Chip verification on hardware accelerator and Software Emulation

Abstract

This paper presents an empirical approach to accelerate the verification of System On Chip using hardware acceleration and software emulation. This paper emphasizes the importance of simultaneous hardware (HW) and Firmware (FW) development to fix HW/SW interaction bugs early in the design to reduce the product development cycle. This paper discusses various solution methodologies for SoC verification methodology using HW emulation & Co-modeling testbench technologies. The test bench is put into the accelerator directly, resulting in a quick migration to accelerator. The functional verification of the SoC and Firmware development is based on Software Oriented Emulation in hardware acceleration mode of testbench technology. The SoC is synthesized on to the Mentor Graphics Veloce2 Quattro Emulation box and U-Boot Monitor Commands are developed with UART and Hyper terminal utility at baud rate of 9600. U-Boot debug monitor commands were customized to debug various verification scenarios and to enable early software development for the SoC. The verification of SoC using U-Boot commands developed and the emulator crystal utilization are presented. The results show that by adopting the accelerated verification on veloce2 emulator using U-Boot software, speedup of the order of 100× was achieved for functional verification of a Complex Multiprocessor SoC compared to standard HDL simulator.