Analog VLSI neural network implementations of hardware annealing and winner-take-all functions

Abstract

Hardware annealing and winner-take-all (WTA) functions have been implemented in 2.0- mu m technology. The hardware annealing technique has been demonstrated using a 4*4 synapse network. Measurement results of a new WTA circuit are presented. The WTA circuit uses transistors biased in saturation to achieve high-speed performance. Since the comparison among the inputs is performed on one common signal line, the circuit can be easily extended to a larger dimension with that common signal line connected throughout the entire circuit. The new high-speed analog winner-take-all circuit can be extended linearly to at least 1024 inputs.<>