Low power frequency doubler

Wing-Kong Ng, Wing-Shan Tam, Chi-Wah Kok
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引用次数: 2

Abstract

A low power frequency doubler circuit that only requires standard CMOS logic gates and on-chip passive components is proposed. The proposed circuit is shown to be compact and has been validated with FPGA implementation. The proposed circuit is found to be robust to wide frequency range and supply voltage variations with excellent frequency and phase performance on high frequency clock generation.

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低功率倍频器
提出了一种只需要标准CMOS逻辑门和片上无源元件的低工频倍频电路。该电路结构紧凑,并通过FPGA实现进行了验证。结果表明,该电路对较宽的频率范围和电源电压变化具有较强的鲁棒性,在高频时钟产生方面具有良好的频率和相位性能。
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