{"title":"A low power and soft error resilience guard-gated Quartro-based flip-flop in 45 nm CMOS technology","authors":"Sabavat Satheesh Kumar, Kumaravel Sundaram, Sanjeevikumar Padmanaban, Jens Bo Holm-Nielsen, Frede Blaabjerg","doi":"10.1049/cds2.12052","DOIUrl":null,"url":null,"abstract":"<p>Conventional flip-flops are more vulnerable to particle strikes in a radiation environment. To overcome this disadvantage, in the literature, many radiation-hardened flip-flops (FFs) based on techniques like triple modular redundancy, dual interlocked cell, Quatro and guard-gated Quatro cell, and so on, are discussed. The flip-flop realized using radiation hardened by design Quatro cell is named as the improved version of Quatro flip-flop (IVQFF). Single event upset (SEU) at inverter stages of master/slave and at output are the two drawbacks of IVQFF. This study proposes a guard-gated Quatro FF (GQFF) using guard-gated Quatro cell and Muller C-element. To overcome the SEU at inverter stages of IVQFF, in GQFF, the inverter stages are realized in a parallel fashion. A dual-input Muller C-element is connected to the GQFF output stage to mask the SEU and thus maintain the correct output. The proposed GQFF tolerates both single node upset (SNU) and double node upset (DNU). It also achieves low power. To prove the efficacy, GQFF and the existing FFs are implemented in 45 nm Complementary Metal Oxide Semiconductor (CMOS) technology. From the simulation results, it may be noted that the GQFF is 100% immune to SNUs and 50% immune to DNUs.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":null,"pages":null},"PeriodicalIF":1.0000,"publicationDate":"2021-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12052","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Iet Circuits Devices & Systems","FirstCategoryId":"5","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1049/cds2.12052","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
Conventional flip-flops are more vulnerable to particle strikes in a radiation environment. To overcome this disadvantage, in the literature, many radiation-hardened flip-flops (FFs) based on techniques like triple modular redundancy, dual interlocked cell, Quatro and guard-gated Quatro cell, and so on, are discussed. The flip-flop realized using radiation hardened by design Quatro cell is named as the improved version of Quatro flip-flop (IVQFF). Single event upset (SEU) at inverter stages of master/slave and at output are the two drawbacks of IVQFF. This study proposes a guard-gated Quatro FF (GQFF) using guard-gated Quatro cell and Muller C-element. To overcome the SEU at inverter stages of IVQFF, in GQFF, the inverter stages are realized in a parallel fashion. A dual-input Muller C-element is connected to the GQFF output stage to mask the SEU and thus maintain the correct output. The proposed GQFF tolerates both single node upset (SNU) and double node upset (DNU). It also achieves low power. To prove the efficacy, GQFF and the existing FFs are implemented in 45 nm Complementary Metal Oxide Semiconductor (CMOS) technology. From the simulation results, it may be noted that the GQFF is 100% immune to SNUs and 50% immune to DNUs.
期刊介绍:
IET Circuits, Devices & Systems covers the following topics:
Circuit theory and design, circuit analysis and simulation, computer aided design
Filters (analogue and switched capacitor)
Circuit implementations, cells and architectures for integration including VLSI
Testability, fault tolerant design, minimisation of circuits and CAD for VLSI
Novel or improved electronic devices for both traditional and emerging technologies including nanoelectronics and MEMs
Device and process characterisation, device parameter extraction schemes
Mathematics of circuits and systems theory
Test and measurement techniques involving electronic circuits, circuits for industrial applications, sensors and transducers