{"title":"一种用于机顶盒的高度集成解码器","authors":"Chiang","doi":"10.1109/ICCE.1997.625961","DOIUrl":null,"url":null,"abstract":"A highly integrated set top box decoder has been designed to meet the challenge of reducing cost while increasing functionality. This decoder is intended to be the heart of the DSS set top box. It incorporates a 32bit ARM CPU, a transport demultiplexer, a MPEG-2 video decoder, a MPEG-1 audio decoder, an NTSC/PAL encoder, an on screen display (OSD) controller to mix graphics and video, a host of U0 interfaces, and an extension bus to connect to other peripherals. This paper analyzes the integration of major functions and the consolidation of separate memories into a single 16 Mbits SDRAM.","PeriodicalId":127085,"journal":{"name":"1997 International Conference on Consumer Electronics","volume":"30 7","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A Highly Integrated Decoder For The Set Top Box\",\"authors\":\"Chiang\",\"doi\":\"10.1109/ICCE.1997.625961\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A highly integrated set top box decoder has been designed to meet the challenge of reducing cost while increasing functionality. This decoder is intended to be the heart of the DSS set top box. It incorporates a 32bit ARM CPU, a transport demultiplexer, a MPEG-2 video decoder, a MPEG-1 audio decoder, an NTSC/PAL encoder, an on screen display (OSD) controller to mix graphics and video, a host of U0 interfaces, and an extension bus to connect to other peripherals. This paper analyzes the integration of major functions and the consolidation of separate memories into a single 16 Mbits SDRAM.\",\"PeriodicalId\":127085,\"journal\":{\"name\":\"1997 International Conference on Consumer Electronics\",\"volume\":\"30 7\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-06-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1997 International Conference on Consumer Electronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCE.1997.625961\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1997 International Conference on Consumer Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCE.1997.625961","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A highly integrated set top box decoder has been designed to meet the challenge of reducing cost while increasing functionality. This decoder is intended to be the heart of the DSS set top box. It incorporates a 32bit ARM CPU, a transport demultiplexer, a MPEG-2 video decoder, a MPEG-1 audio decoder, an NTSC/PAL encoder, an on screen display (OSD) controller to mix graphics and video, a host of U0 interfaces, and an extension bus to connect to other peripherals. This paper analyzes the integration of major functions and the consolidation of separate memories into a single 16 Mbits SDRAM.
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