A new family of power supplies utilizing zero voltage switching (ZVS) has been developed to minimize switching losses and radiated noise. The goals of minimal parts count and low cost were achieved by using a discrete control circuit.
{"title":"A New Family Of Zero Voltage Switching Power Supplies","authors":"Fitzgerald","doi":"10.1109/30.628773","DOIUrl":"https://doi.org/10.1109/30.628773","url":null,"abstract":"A new family of power supplies utilizing zero voltage switching (ZVS) has been developed to minimize switching losses and radiated noise. The goals of minimal parts count and low cost were achieved by using a discrete control circuit.","PeriodicalId":127085,"journal":{"name":"1997 International Conference on Consumer Electronics","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122083126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Custom computers are a new computing paradigm where reconfigurable logic in the form of SRAM-based field programmable gate arrays are used as a co-processor resource in addition to a conventional CPU. This allows application developers to adapt not only the software but also the hardware of the computer on an application-by-application basis. Experimental evaluation of computational speed for 2-D discrete cosine transforms of 8/spl times/8 pixel blocks within a 512/spl times/512 pixel image show that a custom computer can provide speedups of 50-100 times compared to state-of-the art computer workstations, confirming the applicability of custom computing for video processing applications.
{"title":"Video Compression With Custom Computers","authors":"Bergmann, Chung","doi":"10.1109/30.628766","DOIUrl":"https://doi.org/10.1109/30.628766","url":null,"abstract":"Custom computers are a new computing paradigm where reconfigurable logic in the form of SRAM-based field programmable gate arrays are used as a co-processor resource in addition to a conventional CPU. This allows application developers to adapt not only the software but also the hardware of the computer on an application-by-application basis. Experimental evaluation of computational speed for 2-D discrete cosine transforms of 8/spl times/8 pixel blocks within a 512/spl times/512 pixel image show that a custom computer can provide speedups of 50-100 times compared to state-of-the art computer workstations, confirming the applicability of custom computing for video processing applications.","PeriodicalId":127085,"journal":{"name":"1997 International Conference on Consumer Electronics","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121339914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To achieve a single chip solution for a display processor conforming to all DTV formats, various hardwired approaches such as the write end toggle signal (WETS) based design technique and dynamic voltage sensing FIFO architecture have been developed. As a result, all functions including macroblock-to-raster conversion, frame/filed rate conversion, scan format conversion, and ordinary picture making functions such as color interpolation, enhancement, inverse matrix, on screen display, and D/A conversion have been successfully integrated into a single chip. The display processor has a total memory capacity of 284 Kb and filters with a total of 188 taps in an area of 14.9 mm/spl times/14.9 mm. It was fabricated in 0.5 um CMOS technology with 2-metal.
为了实现符合所有数字电视格式的显示处理器的单芯片解决方案，已经开发了各种硬连接方法，例如基于写端切换信号(WETS)的设计技术和动态电压传感FIFO架构。因此，包括宏块到栅格转换、帧/场速率转换、扫描格式转换在内的所有功能，以及颜色插值、增强、逆矩阵、屏幕显示、D/ a转换等普通图像制作功能，都成功地集成在一个芯片上。显示处理器的总存储容量为284 Kb，滤波器在14.9 mm/ sp1倍/14.9 mm的面积上共有188个抽头。它是用2-金属的0.5 um CMOS技术制造的。
{"title":"A Display Processor Conforming To All ATV Formats With 188-tap FIR Filters And 284 Kb FIFO Memories","authors":"Matsuo, Hosotani, Yazawa, Sugawa, Hayashi, Shinohara, Takashima, Okada, Sumi","doi":"10.1109/30.628728","DOIUrl":"https://doi.org/10.1109/30.628728","url":null,"abstract":"To achieve a single chip solution for a display processor conforming to all DTV formats, various hardwired approaches such as the write end toggle signal (WETS) based design technique and dynamic voltage sensing FIFO architecture have been developed. As a result, all functions including macroblock-to-raster conversion, frame/filed rate conversion, scan format conversion, and ordinary picture making functions such as color interpolation, enhancement, inverse matrix, on screen display, and D/A conversion have been successfully integrated into a single chip. The display processor has a total memory capacity of 284 Kb and filters with a total of 188 taps in an area of 14.9 mm/spl times/14.9 mm. It was fabricated in 0.5 um CMOS technology with 2-metal.","PeriodicalId":127085,"journal":{"name":"1997 International Conference on Consumer Electronics","volume":"281 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114139179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A newly developed compact digital auto equalizer and phase locked loop (PLL) system with original algorithms has solved the problems of digital auto equalizer systems using maximum likelihood error (MLE). It realizes experimentally fully automatic and practical size systems. An example of of a corresponding digital VCR is discussed.
{"title":"A Study Of Digital Auto Equalizer And PLL System Using Maximum Likelihood Error For Digital VCRs","authors":"Tonami, Kiyofuji, Suyama","doi":"10.1109/30.628769","DOIUrl":"https://doi.org/10.1109/30.628769","url":null,"abstract":"A newly developed compact digital auto equalizer and phase locked loop (PLL) system with original algorithms has solved the problems of digital auto equalizer systems using maximum likelihood error (MLE). It realizes experimentally fully automatic and practical size systems. An example of of a corresponding digital VCR is discussed.","PeriodicalId":127085,"journal":{"name":"1997 International Conference on Consumer Electronics","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124248199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describe the new extended JPEG coder with variable quantizer using the block wavelet transform which has more flexibility in representing the image dye to a pyramid-like multiresolution decomposition. We replace the discrete cosine transform (DCT) module by block-wise discrete wavelet transform (BDWT) module while keeping all the building blocks of the JPEG extension coder. In addition, we generate the variable quantization matrix (Q-matrix) based on the human visual system (HVS) and utilize the activity of the each block to control the bit and image quality. The simulation results show that the proposed scheme has substantially better performance than the JPEG extensions.
{"title":"The New Extended JPEGg Coder With Variable Quantizer Using Block Wavelet Transform","authors":"Young Huh, Hwang","doi":"10.1109/30.628649","DOIUrl":"https://doi.org/10.1109/30.628649","url":null,"abstract":"This paper describe the new extended JPEG coder with variable quantizer using the block wavelet transform which has more flexibility in representing the image dye to a pyramid-like multiresolution decomposition. We replace the discrete cosine transform (DCT) module by block-wise discrete wavelet transform (BDWT) module while keeping all the building blocks of the JPEG extension coder. In addition, we generate the variable quantization matrix (Q-matrix) based on the human visual system (HVS) and utilize the activity of the each block to control the bit and image quality. The simulation results show that the proposed scheme has substantially better performance than the JPEG extensions.","PeriodicalId":127085,"journal":{"name":"1997 International Conference on Consumer Electronics","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131785847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we determine the number of bits to be used for the encoding of the anchor frame in low bit rate video coding in order to improve the quality of the next and subsequent frames to be encoded. This problem is important in a real time video communication system. We use a progressive method for the transmission of the anchor frame. We develop two methods for determining the optimal number of bits to be allocated to the first frame in on line video communication applications.
{"title":"On The Encoding Of The Anchor Frame In Video Coding","authors":"Kondi, Katsaggelos","doi":"10.1109/30.628614","DOIUrl":"https://doi.org/10.1109/30.628614","url":null,"abstract":"In this paper we determine the number of bits to be used for the encoding of the anchor frame in low bit rate video coding in order to improve the quality of the next and subsequent frames to be encoded. This problem is important in a real time video communication system. We use a progressive method for the transmission of the anchor frame. We develop two methods for determining the optimal number of bits to be allocated to the first frame in on line video communication applications.","PeriodicalId":127085,"journal":{"name":"1997 International Conference on Consumer Electronics","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134525256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Internet-TV was designed and implemented for home users to access the Internet easily using a remote control unit. An original browser suitable for remote control and a lower-resolution TV screen than PCs (personal computers) was developed. In cooperation with a specific Internet provider, a simplified on-line sign-up was implemented to start accessing the Internet immediately.
{"title":"Design And Implementation Of Internet-tv","authors":"Tomari, Saito, Okada, Yoshida","doi":"10.1109/30.628772","DOIUrl":"https://doi.org/10.1109/30.628772","url":null,"abstract":"Internet-TV was designed and implemented for home users to access the Internet easily using a remote control unit. An original browser suitable for remote control and a lower-resolution TV screen than PCs (personal computers) was developed. In cooperation with a specific Internet provider, a simplified on-line sign-up was implemented to start accessing the Internet immediately.","PeriodicalId":127085,"journal":{"name":"1997 International Conference on Consumer Electronics","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115599212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We propose two predictive coding algorithms for 3-D stereo image compression which make use of inter-frame and intra-frame correlation present in stereo image pairs. The predictive coding is applied to one of the two frames associated with each stereo image pair on top of DCT-quantization based compression technology to achieve extra data compression. The technology can also be applied in addition to any other compression technology such as, wavelets based, fractal based, etc. This novel coding technique eliminates the necessity of using overhead bits in reconstructing the predicted image.
{"title":"A Novel Predictive Coding Algorithm For 3-D Image Compression","authors":"Jiang, Edirisinghe, Schroder","doi":"10.1109/30.628653","DOIUrl":"https://doi.org/10.1109/30.628653","url":null,"abstract":"We propose two predictive coding algorithms for 3-D stereo image compression which make use of inter-frame and intra-frame correlation present in stereo image pairs. The predictive coding is applied to one of the two frames associated with each stereo image pair on top of DCT-quantization based compression technology to achieve extra data compression. The technology can also be applied in addition to any other compression technology such as, wavelets based, fractal based, etc. This novel coding technique eliminates the necessity of using overhead bits in reconstructing the predicted image.","PeriodicalId":127085,"journal":{"name":"1997 International Conference on Consumer Electronics","volume":"223 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132499250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a high-performance down scaler to improve the quality of a down-scaled image using interpolation filter. It uses a non-linear phase property of the digital filter to reduce hardware complexity. The implemented architecture is composed of four blocks: (i) line memory, (ii) vertical scaler with interpolation filter, (iii) horizontal scaler with interpolation filter, and (iv) FIFO. It has been fabricated by using 0.65 /spl mu/m CMOS process.
本文提出了一种高性能的降尺度器，利用插值滤波来提高降尺度图像的质量。它利用数字滤波器的非线性相位特性来降低硬件复杂度。实现的架构由四个块组成:(i)行存储器，(ii)带插值滤波器的垂直缩放器，(iii)带插值滤波器的水平缩放器，以及(iv) FIFO。采用0.65 /spl μ m CMOS工艺制备。
{"title":"High Resolution Image Scaler Using Interpolation Filter For Multimedia Video Applications","authors":"Hwang, Sunwoo, Kang, Gerard","doi":"10.1109/30.628720","DOIUrl":"https://doi.org/10.1109/30.628720","url":null,"abstract":"This paper proposes a high-performance down scaler to improve the quality of a down-scaled image using interpolation filter. It uses a non-linear phase property of the digital filter to reduce hardware complexity. The implemented architecture is composed of four blocks: (i) line memory, (ii) vertical scaler with interpolation filter, (iii) horizontal scaler with interpolation filter, and (iv) FIFO. It has been fabricated by using 0.65 /spl mu/m CMOS process.","PeriodicalId":127085,"journal":{"name":"1997 International Conference on Consumer Electronics","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123485929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Neural networks of multi-layer perceptron type perform well as adaptive comb-filters for PAL and NTSC color decoding. They are optimized by learning algorithms. Sampled encoded and original images serve as training patterns.
{"title":"Adaptiver comb-filtering using neural networks","authors":"Prange, Jansen, Horn","doi":"10.1109/30.628727","DOIUrl":"https://doi.org/10.1109/30.628727","url":null,"abstract":"Neural networks of multi-layer perceptron type perform well as adaptive comb-filters for PAL and NTSC color decoding. They are optimized by learning algorithms. Sampled encoded and original images serve as training patterns.","PeriodicalId":127085,"journal":{"name":"1997 International Conference on Consumer Electronics","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125663142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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