{"title":"一种基于浮动门mos的多值联想存储器","authors":"T. Hanyu, T. Higuchi","doi":"10.1109/ISMVL.1991.130700","DOIUrl":null,"url":null,"abstract":"A digit-serial, multiple-valued associative memory VLSI for high-speed information search is presented. Input and output data of a processing element (PE) in the VLSI are directly encoded by appropriate multiple-valued digits, respectively, so that search operations are efficiently described by the combination of a multiple-valued down literals and pass gates. Moreover, multiple-valued memory information is stored in each PE by programming the threshold of the down literal which can be easily implemented using special MOS transistors, called floating-gate MOS transistors. It is demonstrated that the number of interconnections and transistors in the 5-valued associative memory can be reduced to 25% and 53%, respectively, in comparison with the corresponding binary implementation.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"40 3","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A floating-gate-MOS-based multiple-valued associative memory\",\"authors\":\"T. Hanyu, T. Higuchi\",\"doi\":\"10.1109/ISMVL.1991.130700\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A digit-serial, multiple-valued associative memory VLSI for high-speed information search is presented. Input and output data of a processing element (PE) in the VLSI are directly encoded by appropriate multiple-valued digits, respectively, so that search operations are efficiently described by the combination of a multiple-valued down literals and pass gates. Moreover, multiple-valued memory information is stored in each PE by programming the threshold of the down literal which can be easily implemented using special MOS transistors, called floating-gate MOS transistors. It is demonstrated that the number of interconnections and transistors in the 5-valued associative memory can be reduced to 25% and 53%, respectively, in comparison with the corresponding binary implementation.<<ETX>>\",\"PeriodicalId\":127974,\"journal\":{\"name\":\"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic\",\"volume\":\"40 3\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-05-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMVL.1991.130700\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.1991.130700","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A floating-gate-MOS-based multiple-valued associative memory
A digit-serial, multiple-valued associative memory VLSI for high-speed information search is presented. Input and output data of a processing element (PE) in the VLSI are directly encoded by appropriate multiple-valued digits, respectively, so that search operations are efficiently described by the combination of a multiple-valued down literals and pass gates. Moreover, multiple-valued memory information is stored in each PE by programming the threshold of the down literal which can be easily implemented using special MOS transistors, called floating-gate MOS transistors. It is demonstrated that the number of interconnections and transistors in the 5-valued associative memory can be reduced to 25% and 53%, respectively, in comparison with the corresponding binary implementation.<>