Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130734
Frank J. Wroblewski
The inchoate rules of truth of logicism are cohered into the epistemic genesis for mathematics. First the formal truth conditions are exhausted with the complementary indeterminate value, not true and not false. The alternant truth assignments of the determinate Sheffer truth-conferring rules are not exhaustive of the propositional states of affairs necessary for conferring the founding truths. By completing the states-of-affairs assignments, the quantizer axioms reduce to degenerate consequents of Sheffer's rules in the manner of tautologies. The completion is prerequisite for deducing the indeterminate Sheffer truth-conferring rule which continues the bivalent truth tables to trivalence. Undecidability reduces to one of three degrees-of-truth whose alternants include the indeterminate.<>
{"title":"Undecidability in the completion of truth-function logic","authors":"Frank J. Wroblewski","doi":"10.1109/ISMVL.1991.130734","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130734","url":null,"abstract":"The inchoate rules of truth of logicism are cohered into the epistemic genesis for mathematics. First the formal truth conditions are exhausted with the complementary indeterminate value, not true and not false. The alternant truth assignments of the determinate Sheffer truth-conferring rules are not exhaustive of the propositional states of affairs necessary for conferring the founding truths. By completing the states-of-affairs assignments, the quantizer axioms reduce to degenerate consequents of Sheffer's rules in the manner of tautologies. The completion is prerequisite for deducing the indeterminate Sheffer truth-conferring rule which continues the bivalent truth tables to trivalence. Undecidability reduces to one of three degrees-of-truth whose alternants include the indeterminate.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124845071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130756
M. Sasaki, F. Ueno
A fuzzy logic function generator (FLUG) based on the singleton fuzzy control algorithm is proposed. The normalizing operation can be removed from the original algorithm by introducing a new t-norm operation. The FLUG can be simply implemented with the current mode CMOS circuits, because the dividers are not needed. Further, to solve the problem in the current mode with respect to the restriction of the fan-out number, voltage-input, and current-output membership function circuits are constituted of operational transconductance amplifiers (OTAs), and they are used in the input parts of the FLUG. Due to the simple circuitry, the FLUG can be applied to a basic cell for the analog application-specific ICs.<>
{"title":"A fuzzy logic function generator (FLUG) implemented with current mode CMOS circuits","authors":"M. Sasaki, F. Ueno","doi":"10.1109/ISMVL.1991.130756","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130756","url":null,"abstract":"A fuzzy logic function generator (FLUG) based on the singleton fuzzy control algorithm is proposed. The normalizing operation can be removed from the original algorithm by introducing a new t-norm operation. The FLUG can be simply implemented with the current mode CMOS circuits, because the dividers are not needed. Further, to solve the problem in the current mode with respect to the restriction of the fan-out number, voltage-input, and current-output membership function circuits are constituted of operational transconductance amplifiers (OTAs), and they are used in the input parts of the FLUG. Due to the simple circuitry, the FLUG can be applied to a basic cell for the analog application-specific ICs.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126607415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130742
Tsutomu Sasao
A transformation for p-valued input functions is presented. The number of products in minimum exclusive-or sum-of-products expressions (ESOPs) is invariant under this transformation. Algorithms for reducing the number of product terms in ESOPs using this transformation are presented for p=2 and p=4. Arithmetic functions are simplified to show the ability of this approach.<>
{"title":"A transformation of multiple-valued input two-valued output functions and its application to simplification of exclusive-or sum-of-products expressions","authors":"Tsutomu Sasao","doi":"10.1109/ISMVL.1991.130742","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130742","url":null,"abstract":"A transformation for p-valued input functions is presented. The number of products in minimum exclusive-or sum-of-products expressions (ESOPs) is invariant under this transformation. Algorithms for reducing the number of product terms in ESOPs using this transformation are presented for p=2 and p=4. Arithmetic functions are simplified to show the ability of this approach.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114203500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130714
R. Tosic, I. Stojmenovic, M. Miyakawa
The symmetric functions of m-valued logic have a sum-product (i.e. max-min) representation whose terms are sums of fundamental symmetric functions (FSFs). These sums may be simplified if they contain adjacent SFSs. This naturally leads to the combinatorial problem of determining the maximum size M(m,n) of adjacent-free sets of n-variable SFSs. J.C. Muzio (1990) related M(m,n) to a special graph F(m,n). Continuing in this direction, the authors give a simple closed formula for M(m,n) and then deduce that for large m or large n the largest nonsimplifiable set of n-variable SFSs consists of approximately one-half of all possible FSFs, proving thus also all the conjectures from the Muzio paper (see Proc. 20th Int. Symp. on Multiple-Valued Logic, p.292-9 (1990).).<>
{"title":"On the maximum size of the terms in the realization of symmetric functions","authors":"R. Tosic, I. Stojmenovic, M. Miyakawa","doi":"10.1109/ISMVL.1991.130714","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130714","url":null,"abstract":"The symmetric functions of m-valued logic have a sum-product (i.e. max-min) representation whose terms are sums of fundamental symmetric functions (FSFs). These sums may be simplified if they contain adjacent SFSs. This naturally leads to the combinatorial problem of determining the maximum size M(m,n) of adjacent-free sets of n-variable SFSs. J.C. Muzio (1990) related M(m,n) to a special graph F(m,n). Continuing in this direction, the authors give a simple closed formula for M(m,n) and then deduce that for large m or large n the largest nonsimplifiable set of n-variable SFSs consists of approximately one-half of all possible FSFs, proving thus also all the conjectures from the Muzio paper (see Proc. 20th Int. Symp. on Multiple-Valued Logic, p.292-9 (1990).).<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121617793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130698
Y. Yuminaka, T. Aoki, T. Higuchi
An ultra-higher-valued logic network, called a set logic network, is proposed to provide a potential solution to the interconnection problems in VLSI systems. The basic concept is frequency multiplexing of logic values for the increase of information density in logic networks. It is shown that the set logic network can be constructed with only two basic building blocks realized by frequency-selective analog circuits. Its application to a parallel image processor is discussed based on functional multiplexing of binary modules into a single set logic module. A great reduction of interconnections can be achieved by using an optimal multiplexing scheme.<>
{"title":"Design of a set logic network based on frequency multiplexing and its applications to image processing","authors":"Y. Yuminaka, T. Aoki, T. Higuchi","doi":"10.1109/ISMVL.1991.130698","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130698","url":null,"abstract":"An ultra-higher-valued logic network, called a set logic network, is proposed to provide a potential solution to the interconnection problems in VLSI systems. The basic concept is frequency multiplexing of logic values for the increase of information density in logic networks. It is shown that the set logic network can be constructed with only two basic building blocks realized by frequency-selective analog circuits. Its application to a parallel image processor is discussed based on functional multiplexing of binary modules into a single set logic module. A great reduction of interconnections can be achieved by using an optimal multiplexing scheme.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131593077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130759
M. Abd-El-Barr, H. Choy, A. K. Jain, R. Bolton
Four programmable structures have been proposed earlier for realization of multivalued multithreshold (MVMT) functions. Each of these structures consists of repeated modules each of which realizes either a unit step function or a staircase function. Two structures for realization of MVMT functions are introduced which are shown to be superior to existing structures in terms of the chip-pin count needed and the chip area are consumed. A comparative study of three programmable structures is provided in terms of these two measures. The basis for the comparison is the set of four-, six-, and eight-valued three- to six-threshold functions.<>
{"title":"A comparative study of programmable realization techniques of multi-valued multi-threshold functions","authors":"M. Abd-El-Barr, H. Choy, A. K. Jain, R. Bolton","doi":"10.1109/ISMVL.1991.130759","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130759","url":null,"abstract":"Four programmable structures have been proposed earlier for realization of multivalued multithreshold (MVMT) functions. Each of these structures consists of repeated modules each of which realizes either a unit step function or a staircase function. Two structures for realization of MVMT functions are introduced which are shown to be superior to existing structures in terms of the chip-pin count needed and the chip area are consumed. A comparative study of three programmable structures is provided in terms of these two measures. The basis for the comparison is the set of four-, six-, and eight-valued three- to six-threshold functions.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131015263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130722
C. Rozon, H. Mouftah
The testability of ternary CMOS gates was examined in order to find suitable test vectors to detect stuck-at, stuck-open, and stuck-short faults. A two-level fault model approach was used: a transistor-by-transistor model for low component count operators and a gate-level model for large component count operators. Results are given in a tabular format for each gate. Since these ternary CMOS circuits operate on the set (0,1,2) compared to similar CMOS binary circuits which operate on the set
{"title":"Testability analysis of CMOS ternary circuits","authors":"C. Rozon, H. Mouftah","doi":"10.1109/ISMVL.1991.130722","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130722","url":null,"abstract":"The testability of ternary CMOS gates was examined in order to find suitable test vectors to detect stuck-at, stuck-open, and stuck-short faults. A two-level fault model approach was used: a transistor-by-transistor model for low component count operators and a gate-level model for large component count operators. Results are given in a tabular format for each gate. Since these ternary CMOS circuits operate on the set (0,1,2) compared to similar CMOS binary circuits which operate on the set","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123344389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130710
Tatsuki Watanabe, M. Matsumoto
An application of the synchronous fuzzy sequential system to pattern recognition in which fuzzy propositions are used to represent various sizes of circles is presented. The advantages of the proposed system include the small amount of required memory elements as well as a fast recognition speed caused by the sequential procedure. Furthermore, an easy realization of the system with electronic devices can be expected because of the simplicity of the fuzzy set operations. The simulation results for some examples are shown.<>
{"title":"Recognition of circle form using fuzzy sequential system","authors":"Tatsuki Watanabe, M. Matsumoto","doi":"10.1109/ISMVL.1991.130710","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130710","url":null,"abstract":"An application of the synchronous fuzzy sequential system to pattern recognition in which fuzzy propositions are used to represent various sizes of circles is presented. The advantages of the proposed system include the small amount of required memory elements as well as a fast recognition speed caused by the sequential procedure. Furthermore, an easy realization of the system with electronic devices can be expected because of the simplicity of the fuzzy set operations. The simulation results for some examples are shown.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125256790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130720
Konrad Lei, Z. Vranesic
Synthesis of 4-valued current mode CMOS circuits is considered. A method for deriving low-cost realizations of single-variable functions, based on the incremental cost approach, is presented. A technique for synthesis of 2-variable functions, incorporating a modified direct cover approach, is considered. The results show that this technique can be used effectively in conjunction with the multiplexer-circuit synthesis method.<>
{"title":"On the synthesis of 4-valued current mode CMOS circuits","authors":"Konrad Lei, Z. Vranesic","doi":"10.1109/ISMVL.1991.130720","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130720","url":null,"abstract":"Synthesis of 4-valued current mode CMOS circuits is considered. A method for deriving low-cost realizations of single-variable functions, based on the incremental cost approach, is presented. A technique for synthesis of 2-variable functions, incorporating a modified direct cover approach, is considered. The results show that this technique can be used effectively in conjunction with the multiplexer-circuit synthesis method.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132123098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-26DOI: 10.1109/ISMVL.1991.130708
L. Godo, F. Esteva, P. Garcia-Calvés, J. Agustí-Cullell
A formal semantical approach to fuzzy logic is given, formalizing it as a family of institutions. In this frame the soundness of the most-used inference patterns in fuzzy logic is proved. The authors believe that this formalization of fuzzy logic can be used to prove the soundness of other inference patterns such as the principle of resolution or the chaining inference rule.<>
{"title":"A formal semantical approach to fuzzy logic","authors":"L. Godo, F. Esteva, P. Garcia-Calvés, J. Agustí-Cullell","doi":"10.1109/ISMVL.1991.130708","DOIUrl":"https://doi.org/10.1109/ISMVL.1991.130708","url":null,"abstract":"A formal semantical approach to fuzzy logic is given, formalizing it as a family of institutions. In this frame the soundness of the most-used inference patterns in fuzzy logic is proved. The authors believe that this formalization of fuzzy logic can be used to prove the soundness of other inference patterns such as the principle of resolution or the chaining inference rule.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114381652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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