系统级设计环境中半形式化验证的自省机制

M. Metzger, F. Bastien, F. Rousseau, J. Vachon, E. Aboulhamid
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引用次数: 3

摘要

新一代的CAD工具是必要的,以应付日益复杂的片上系统。我们认为,它们应该建立在一个现代和标准的框架之上。ESys。.NET是一个基于。NET框架的设计环境。它利用了先进的编程特性,方便了外部工具的集成。本文提出了一个ESys.NET的半形式化验证工具。内省能力以及与第三方工具的协作能力都得到了强调。自省用于在模拟期间检索模型的状态,并检查一组用户定义的规则。验证过程既不修改模型,也不修改模拟器。在AMBA总线模型上的实验验证了该方法的有效性
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Introspection Mechanisms for Semi-Formal Verification in a System-Level Design Environment
A new generation of CAD tools is mandatory to cope with the growing complexity of system-on-chip. We believe that they should be built on top of a modern and standard framework. ESys.NET is a design environment based on the .NET framework. It takes advantage of advanced programming features which facilitates the integration of external tools. This paper presents a semi-formal verification tool for ESys.NET. Introspection ability is emphasized together with its capabilities to cooperate with third party tools. Introspection is used to retrieve the state of the model during simulation and to check a set of user defined rules. Neither the model nor the simulator is modified by the verification process. Experimentations on an AMBA bus model highlight the effectiveness of this approach
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